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Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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Bibliographic References
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Refworks Procite/RefMan
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
April 07-April 10
ISBN: 978-0-7695-3098-7
Table of Contents
Papers
Cover Art
(PDF)
pp. c1
ABSTRACT
PDF
Title Page i
(PDF)
pp. i
ABSTRACT
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Title Page iii
(PDF)
pp. iii
ABSTRACT
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Copyright Page
(PDF)
pp. iv
ABSTRACT
PDF
Table of Contents
(PDF)
pp. v-viii
ABSTRACT
PDF
Message from General Chair(s)
(PDF)
pp. ix-x
ABSTRACT
PDF
Organizing Committee
(PDF)
pp. xi
ABSTRACT
PDF
Program Committee
(PDF)
pp. xii
ABSTRACT
PDF
Reviewers
(PDF)
pp. xiii
ABSTRACT
PDF
Invited Talk 1- Past, Present, and Future Communicating Processors
(PDF)
David May
pp. xiv
ABSTRACT
PDF
Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip Photonics
(PDF)
Ian H White
Richard V. Penty
pp. xv
ABSTRACT
PDF
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
(Abstract)
Bart Vermeulen
Kees Goossens
Siddharth Umrani
pp. 3-12
ABSTRACT
PDF
PURCHASE ARTICLE: $19
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
(Abstract)
Michihiro Koibuchi
Hiroki Matsutani
Hideharu Amano
Timothy Mark Pinkston
pp. 13-22
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
(Abstract)
Hiroki Matsutani
Michihiro Koibuchi
Daihan Wang
Hideharu Amano
pp. 23-32
ABSTRACT
PDF
PURCHASE ARTICLE: $19
A Network of Time-Division Multiplexed Wiring for FPGAs
(Abstract)
Rosemary Francis
Simon Moore
Robert Mullins
pp. 35-44
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
(Abstract)
Kees Goossens
Martijn Bennebroek
Jae Young Hur
Muhammad Aqeel Wahlah
pp. 45-54
ABSTRACT
PDF
PURCHASE ARTICLE: $19
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
(Abstract)
Mikkel Bystrup Stensgaard
Jens Spars?
pp. 55-64
ABSTRACT
PDF
PURCHASE ARTICLE: $19
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
(Abstract)
Alireza Ejlali
Bashir M. Al-Hashimi
pp. 67-76
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
(Abstract)
Po-Tsang Huang
Wei-Li Fang
Yin-Ling Wang
Wei Hwang
pp. 77-83
ABSTRACT
PDF
PURCHASE ARTICLE: $19
An Efficient Implementation of Distributed Routing Algorithms for NoCs
(Abstract)
Jos? Flich
Samuel Rodrigo
Jos? Duato
pp. 87-96
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms
(Abstract)
Maurizio Palesi
Giuseppe Longo
Salvatore Signorino
Rickard Holsmark
Shashi Kumar
Vincenzo Catania
pp. 97-106
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework
(Abstract)
Francisco Gilabert
Simone Medardoni
Davide Bertozzi
Luca Benini
Mar?a Engracia Gomez
Pedro Lopez
Jos? Duato
pp. 107-116
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
(Abstract)
Bin Li
Li-Shiuan Peh
Priyadarsan Patra
pp. 117-126
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
(Abstract)
E. Beign?
F. Clermidy
S. Miermont
P. Vivet
pp. 129-138
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
(Abstract)
Ivan Miro-Panades
Fabien Clermidy
Pascal Vivet
Alain Greiner
pp. 139-148
ABSTRACT
PDF
PURCHASE ARTICLE: $19
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application
(Abstract)
Xuan-Tu Tran
Yvain Thonnart
Jean Durupt
Vincent Beroulle
Chantal Robach
pp. 149-158
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
(Abstract)
Zheng Shi
Alan Burns
pp. 161-170
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Statistical Approach to NoC Design
(Abstract)
Itamar Cohen
Ori Rottenstreich
Isaac Keslassy
pp. 171-180
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Reducing the Interconnection Network Cost of Chip Multiprocessors
(Abstract)
Pablo Abad
Valentin Puente
Jose Angel Gregorio
pp. 183-192
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Circuit-Switched Coherence
(Abstract)
Natalie D. Enright Jerger
Li-Shiuan Peh
Mikko H. Lipasti
pp. 193-202
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network
(Abstract)
S. Suboh
M. Bakhouya
T. El-Ghazawi
pp. 205-206
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip
(Abstract)
Min Zhang
Chiu-Sing Choy
pp. 207-208
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Network Simplicity for Latency Insensitive Cores
(Abstract)
Daniel Gebhardt
JunBok You
W. Scott Lee
Kenneth S. Stevens
pp. 209-210
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
(Abstract)
Andreas Hansson
Maarten Wiggers
Arno Moonen
Kees Goossens
Marco Bekooij
pp. 211-212
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Implementation of Wave-Pipelined Interconnects in FPGAs
(Abstract)
Terrence Mak
Crescenzo D'Alessandro
Pete Sedcole
Peter Y.K. Cheung
Alex Yakovlev
Wayne Luk
pp. 213-214
ABSTRACT
PDF
PURCHASE ARTICLE: $19
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
(Abstract)
Luis A. Plana
John Bainbridge
Steve Furber
Sean Salisbury
Yebin Shi
Jian Wu
pp. 215-216
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Dual-Channel Access Mechanism for Cost-Effective NoC Design
(Abstract)
Shijun Lin
Li Su
Depeng Jin
Lieguang Zeng
pp. 217-218
ABSTRACT
PDF
PURCHASE ARTICLE: $19
Author Index
(PDF)
pp. 219-220
ABSTRACT
PDF
Roster
(PDF)
pp. 222
ABSTRACT
PDF
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