Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu, "An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator," Networks-on-Chip, International Symposium on, pp. 215-216, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008.

@article{ 10.1109/NOCS.2008.30,
author = {Luis A. Plana and John Bainbridge and Steve Furber and Sean Salisbury and Yebin Shi and Jian Wu},
title = {An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator},
journal ={Networks-on-Chip, International Symposium on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3098-7},
pages = {215-216},
doi = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.30},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - Networks-on-Chip, International Symposium on
TI - An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
SN - 978-0-7695-3098-7
SP215
EP216
A1 - Luis A. Plana,
A1 - John Bainbridge,
A1 - Steve Furber,
A1 - Sean Salisbury,
A1 - Yebin Shi,
A1 - Jian Wu,
PY - 2008
KW - GALS
KW - Synchonizer
KW - Bandwidth aggregation
KW - source-address routing
VL - 0
JA - Networks-on-Chip, International Symposium on
ER -