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First International Symposium on Networks-on-Chip (NOCS'07)
Princeton, New Jersey
May 07-May 09
ISBN: 0-7695-2773-6
Table of Contents
Introduction
Tutorial: Networks on Chips
Network Layer Protocols and Performance Analysis
Power, Energy and Reliability Issues in NoC
Tooling, OS Services and Middleware
Keynote 1
Session 1: NoC Design Case Studies
Paul Gratz, The University of Texas at Austin, USA
Karthikeyan Sankaralingam, The University of Texas at Austin, USA
Heather Hanson, The University of Texas at Austin, USA
Premkishore Shivakumar, The University of Texas at Austin, USA
Robert McDonald, The University of Texas at Austin, USA
Stephen W. Keckler, The University of Texas at Austin, USA
Doug Burger, The University of Texas at Austin, USA
pp. 7-17
Thomas William Ainsworth, University of Southern California Los Angeles, USA
Timothy Mark Pinkston, University of Southern California Los Angeles, USA
pp. 18-29
Donghyun Kim, Korea Advanced Institute of Science and Technology (KAIST), Korea
Kwanho Kim, Korea Advanced Institute of Science and Technology (KAIST), Korea
Joo-Young Kim, Korea Advanced Institute of Science and Technology (KAIST), Korea
Seung-Jin Lee, Korea Advanced Institute of Science and Technology (KAIST), Korea
Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology (KAIST), Korea
pp. 30-39
Jeff Hoffman, Intel Corporation, California, USA
David Arditti Ilitzky, Intel Corporation, California, USA
Anthony Chun, Intel Corporation, California, USA
Aliaksei Chapyzhenka, Intel Corporation, California, USA
pp. 40-52
Session 2: Technology and Circuit Technologies
Assaf Shacham, Columbia University, USA
Keren Bergman, Columbia University, USA
Luca P. Carloni, Columbia University, USA
pp. 53-64
Crescenzo D'Alessandro, Newcastle University, UK
Nikolaos Minas, Newcastle University, UK
Keith Heron, Newcastle University, UK
David Kinniment, Newcastle University, UK
Alex Yakovlev, Newcastle University, UK
pp. 65-74
Shuming Chen, National University of Defense Technology, China
Xiangyuan Liu, National University of Defense Technology, China
pp. 75-82
Session 3: System Architecture, Verification and Debug
Kees Goossens, NXP Semiconductors, The Netherlands; Technical University Delft, The Netherlands
Bart Vermeulen, NXP Semiconductors, The Netherlands
Remco van Steeden, Technical University of Twente, The Netherlands
Martijn Bennebroek, Research, Philips, The Netherlands
pp. 95-106
T. Marescaux, IMEC, Belgium
E. Brockmeyer, IMEC, Belgium
H. Corporaal, Technical University Eindhoven, The Netherlands
pp. 107-116
Evgeny Bolotin, Israel Institute of Technology, Israel
Zvika Guz, Israel Institute of Technology, Israel
Israel Cidon, Israel Institute of Technology, Israel
Ran Ginosar, Israel Institute of Technology, Israel
Avinoam Kolodny, Israel Institute of Technology, Israel
pp. 117-126
Dominique Borrione, TIMA Laboratory-INPG, France
Amr Helmy, TIMA Laboratory-INPG, France
Laurence Pierre, TIMA Laboratory-INPG, France
Julien Schmaltz, Saarland University, Germany
pp. 127-136
Isask'har Walter, Israel Institute of Technology, Israel
Israel Cidon, Israel Institute of Technology, Israel
Ran Ginosar, Israel Institute of Technology, Israel
Avinoam Kolodny, Israel Institute of Technology, Israel
pp. 137-148
Keynote 2
Session 4: Routing and Topology
George Michelogiannakis, Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
Dionisios Pnevmatikatos, Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
Manolis Katevenis, Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
pp. 153-162
Arnab Banerjee, University of Cambridge, UK
Robert Mullins, University of Cambridge, UK
Simon Moore, University of Cambridge, UK
pp. 163-172
Terrence S.T. Mak, Imperial College London, UK
Pete Sedcole, Imperial College London, UK
Peter Y.K. Cheung, Imperial College London, UK
Wayne Luk, Imperial College London, UK
K.P. Lam, The Chinese University of Hong Kong, Hong Kong
pp. 173-182
J. Flich, Universidad Politecnica de Valencia, Spain
A. Mejia, Universidad Politecnica de Valencia, Spain
P. Lopez, Universidad Politecnica de Valencia, Spain
J. Duato, Universidad Politecnica de Valencia, Spain
pp. 183-194
Panel Session
Cristian Grecu, University of British Columbia
Andre Ivanov, University of British Columbia
Partha Pande, Washington State University
Axel Jantsch, Royal Institute of Technology
Erno Salminen, Tampere University of Technology
Umit Ogras, Carnegie Mellon University
Radu Marculescu, Carnegie Mellon University
pp. 205
Poster Session
Per Badlund, Royal Institute of Technology, Sweden
Axel Jantsch, Royal Institute of Technology, Sweden
pp. 215
Xuan-Tu Tran, CEA-LETI, France
Jean Durupt, CEA-LETI, France
Yvain Thonnart, CEA-LETI, France
Francois Bertrand, CEA-LETI, France
Vincent Beroulle, INPG-LCIS, France
Chantal Robach, INPG-LCIS, France
pp. 216
Mikael Millberg, KTH-Royal Institute of Technology, Sweden
Axel Jantsch, KTH-Royal Institute of Technology, Sweden
pp. 217
Rostislav (Reuven) Dobkin, Israel Institute of Technology, Israel
Ran Ginosar, Israel Institute of Technology, Israel
Israel Cidon, Israel Institute of Technology, Israel
pp. 218
Simon Ogg, University of Southampton, UK
Enrico Valli, University of Bologna
Crescenzo D'Alessandro, Newcastle University, UK
Alex Yakovlev, Newcastle University, UK
Bashir Al-Hashimi, University of Southampton, UK
Luca Benini, University of Bologna
pp. 219
Sheng Xu, University of Massachusetts Amherst, USA
Ibis Benito, University of Massachusetts Amherst, USA
Wayne Burleson, University of Massachusetts Amherst, USA
pp. 220
Session 5: Reconfigurable NoCs
Jean-Philippe Diguet, Universite de Bretagne Sud/CNRS, France
Samuel Evain, Universite de Bretagne Sud/CNRS, France
Romain Vaslin, Universite de Bretagne Sud/CNRS, France
Guy Gogniat, Universite de Bretagne Sud/CNRS, France
Emmanuel Juin, Universite de Bretagne Sud/CNRS, France
pp. 223-232
Andreas Hansson, Eindhoven University of Technology, The Netherlands
Kees Goossens, Delft University of Technology, The Netherlands; NXP Semiconductors, The Netherlands
pp. 233-242
Zied Marrakchi, LIP6, Universite Pierre et Marie Curie, France
Hayder Mrabet, LIP6, Universite Pierre et Marie Curie, France
Christian Masson, LIP6, Universite Pierre et Marie Curie, France
Habib Mehrez, LIP6, Universite Pierre et Marie Curie, France
pp. 243-252
Roman Gindin, Israel Institute of Technology, Israel
Israel Cidon, Israel Institute of Technology, Israel
Idit Keidar, Israel Institute of Technology, Israel
pp. 253-264
Dinner Speaker
Keynote 3
Israel Cidon, Israel Institute of Technology, Israel
pp. 269
Session 6: CAD and Methodology for NoCs
Antonio Pullini, Politecnico di Torino, Italy
Federico Angiolini, University of Bologna, Italy
Paolo Meloni, University of Cagliari, Italy
David Atienza, LSI, EPFL, Switzerland; Complutense University, Spain
Srinivasan Murali, Stanford University, California, USA
Luigi Raffo, University of Cagliari, Italy
Giovanni De Micheli, LSI, EPFL, Switzerland
Luca Benini, University of Bologna, Italy
pp. 273-282
Daniel Greenfield, University of Cambridge, UK
Arnab Banerjee, University of Cambridge, UK
Jeong-Gun Lee, University of Cambridge, UK
Simon Moore, University of Cambridge, UK
pp. 283-294
Session 7: NoC Mapping and Simulation
Wein-Tsung Shen, National Taiwan University, Taiwan
Chih-Hao Chao, National Taiwan University, Taiwan
Yu-Kuang Lien, National Taiwan University, Taiwan
An-Yeu (Andy) Wu, National Taiwan University, Taiwan
pp. 317-322
Pascal T. Wolkotte, University of Twente, The Netherlands
Philip K.F. Holzenspies, University of Twente, The Netherlands
Gerard J.M. Smit, University of Twente, The Netherlands
pp. 323-332
Author Index
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