CSDL - Proceedings M

M
MTV
2007
2007 Eighth International Workshop on Microprocessor Test and Verification

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2007 Eighth International Workshop on Microprocessor Test and Verification

December 05-December 06

ISBN: 978-0-7695-3241-7

Table of Contents

Papers

Cover Art (PDF)

pp. C4,C1

ABSTRACT

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Title Page i (PDF)

pp. i

ABSTRACT

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Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-vi

ABSTRACT

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Preface (PDF)

pp. vii

ABSTRACT

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Acknowledgment (PDF)

pp. viii

ABSTRACT

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Committees (PDF)

pp. ix-x

ABSTRACT

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Assertion-Based Modal Power Estimation (Abstract)

Sumit Ahuja

Deepak A. Mathaikutty

Sandeep Shukla

Ajit Dingankar

pp. 3-7

ABSTRACT

PDF

PURCHASE ARTICLE: $19

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Early Models for System-Level Power Estimation (Abstract)

pp. 8-14

PDF

PURCHASE ARTICLE: $19

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Reduction of Power Dissipation during Scan Testing by Test Vector Ordering (Abstract)

Wang-Dauh Tseng

Lung-Jen Lee

pp. 15-21

ABSTRACT

PDF

PURCHASE ARTICLE: $19

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Mechanized Certification of Secure Hardware Designs (Abstract)

Sandip Ray

Warren A. Hunt Jr.

pp. 25-32

ABSTRACT

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PURCHASE ARTICLE: $19

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Application of Lifting in Partial Design Analysis (Abstract)

pp. 33-38

PDF

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Model Checking Bluespec Specified Hardware Designs (Abstract)

Gaurav Singh

Sandeep K. Shukla

pp. 39-43

ABSTRACT

PDF

PURCHASE ARTICLE: $19

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Runtime Verification of k-Mutual Exclusion for SoCs (Abstract)

Selma Ikiz

Alper Sen

pp. 44-50

ABSTRACT

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A Scalable Symbolic Simulator for Verilog RTL (Abstract)

Sasidhar Sunkari

Supratik Chakraborty

Vivekananda Vedula

Kailasnath Maneparambil

pp. 51-59

ABSTRACT

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PURCHASE ARTICLE: $19

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Top Level SOC Interconnectivity Verification Using Formal Techniques (Abstract)

Subir K. Roy

pp. 63-70

ABSTRACT

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On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction (Abstract)

pp. 71-76

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Automotive Microcontroller End-of-Line Test via Software-Based Methodologies (Abstract)

pp. 77-82

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Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning (Abstract)

pp. 85-90

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Chico: An On-chip Hardware Checker for Pipeline Control Logic (Abstract)

pp. 91-97

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A CLP-Based Functional ATPG for Extended FSMs (Abstract)

pp. 98-105

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Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits (Abstract)

pp. 109-115

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An ADL for Functional Specification of IA32 (Abstract)

Wei Qin

Asa Ben-Tzur

Boris Gutkovich

pp. 119-127

ABSTRACT

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PURCHASE ARTICLE: $19

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Automatic Testbench Generation for Rearchitected Designs (Abstract)

Mark Nodine

pp. 128-136

ABSTRACT

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Author Index (PDF)

pp. 137

ABSTRACT

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Publisher's Information (PDF)

pp. 138

ABSTRACT

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