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Fifth International Workshop on Microprocessor Test and Verification (MTV'04) (2005)
Austin, Texas
Nov. 3, 2005 to Nov. 5, 2005
ISBN: 0-7695-2627-6
TABLE OF CONTENTS
Introduction
Preface (PDF)
pp. vii
pp. viii
Architecture Description Languages
Wei Qin , Boston University, USA
Sharad Malik , Princeton University, USA
pp. 3-11
Brian Kahne , Freescale Semiconductor Inc, USA
Aseem Gupta , University of California, Irvine, USA
Peter Wilson , Freescale Semiconductor Inc, USA
Nikil Dutt , University of California, Irvine, USA
pp. 12-22
SAT Applications
Marc Herbstritt , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 23-28
Tobias Schubert , Albert-Ludwigs-University of Freiburg, Germany
Matthew Lewis , Albert-Ludwigs-University of Freiburg, Germany
Bernd Becker , Albert-Ludwigs-University of Freiburg, Germany
pp. 29-36
Debug and Diagnosis
P. Bernardi , Politecnico di Torino, Italy
E. Sanchez , Politecnico di Torino, Italy
M. Schillaci , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
G. Squillero , Politecnico di Torino, Italy
pp. 37-41
Moayad Fahim Ali , University of Toronto, Canada
Sean Safarpour , University of Toronto, Canada
Andreas Veneris , University of Toronto, Canada
Magdy S. Abadir , Freescale Semiconductor, USA
Rolf Drechsler , University of Bremen, Germany
pp. 42-47
P. Bernardi , Politecnico di Torino, Italy
M. Grosso , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 55-62
High Level Test and ATPG
Bin Xue , Intel Corp., USA
D. M. H. Walker , Texas A&M University, USA
pp. 63-69
G. Di Guglielmo , Universita di Verona, Italy
F. Fummi , Universita di Verona, Italy
C. Marconcini , Universita di Verona, Italy
G. Pravadelli , Universita di Verona, Italy
pp. 70-75
Charles H.-P. Wen , University of California, Santa Barbara, USA
Li-C. Wang , University of California, Santa Barbara, USA
pp. 76-83
Jorge Campos , University of California, Davis, USA
Hussain Al-Asaad , University of California, Davis, USA
pp. 84-89
John Mark Nolen , Texas A&M University, USA
Rabi Mahapatra , Texas A&M University, USA
pp. 90-98
Validation
David Berner , Institut de Recherche en Informatique et Systemes Aleatoires (IRISA/INRIA), France
Hiren D. Patel , Virginia Polytechnic and State University, USA
Deepak A. Mathaikutty , Virginia Polytechnic and State University, USA
Sandeep K. Shukla , Virginia Polytechnic and State University, USA
pp. 99-104
Jayanta Bhadra , Freescale Semiconductor Inc., USA
Magdy S. Abadir , Freescale Semiconductor Inc., USA
David Burgess , Freescale Semiconductor Inc., USA
Ekaterina Trofimova , Freescale Semiconductor Inc., USA
pp. 111-118
Prabhat Mishra , University of Florida, USA
Heon-Mo Koo , University of Florida, USA
Zhuo Huang , University of Florida, USA
pp. 119-126
Advances in Verification Methodology for Complex Designs
Nicola Bombieri , TMicroelectronics, Italy
Andrea Fedeli , TMicroelectronics, Italy
Franco Fummi , University of Verona, Italy
pp. 127-132
Daniel Gro?e , University of Bremen, Germany
Ulrich K? , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 133-137
Brian Kahne , Freescale Semiconductor Inc, USA
Magdy Abadir , Freescale Semiconductor Inc, USA
pp. 138-142
Author Index
Author Index (PDF)
pp. 143
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