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Sixth International Workshop on Microprocessor Test and Verification (MTV'05)
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors
Austin, Texas
November 03-November 05
ISBN: 0-7695-2627-6
| ASCII Text | x | ||
| Soohong P. Kim, "Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors," Fifth International Workshop on Microprocessor Test and Verification (MTV'04), pp. 105-110, Sixth International Workshop on Microprocessor Test and Verification (MTV'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/MTV.2005.19, author = {Soohong P. Kim}, title = {Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors}, journal ={Fifth International Workshop on Microprocessor Test and Verification (MTV'04)}, volume = {0}, year = {2005}, issn = {1550-4093}, pages = {105-110}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTV.2005.19}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Fifth International Workshop on Microprocessor Test and Verification (MTV'04) TI - Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors SN - 1550-4093 SP105 EP110 A1 - Soohong P. Kim, PY - 2005 KW - null VL - 0 JA - Fifth International Workshop on Microprocessor Test and Verification (MTV'04) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTV.2005.19
This paper presents a pre-silicon validation methodology of Intel? Itanium? Processor Family (IPF) memory ordering [2] for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-Silicon validation stage.
Citation:
Soohong P. Kim, "Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors," mtv, pp.105-110, Sixth International Workshop on Microprocessor Test and Verification (MTV'05), 2005
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