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2007 IEEE International Workshop on Memory Technology, Design and Testing
System-in-Package design/testing in memory package
Taipei, Taiwan
December 03-December 05
ISBN: 978-1-4244-1656-1
| ASCII Text | x | ||
| Scott Chen, "System-in-Package design/testing in memory package," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 1, 2007 IEEE International Workshop on Memory Technology, Design and Testing, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/MTDT.2007.4547601, author = {Scott Chen}, title = {System-in-Package design/testing in memory package}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2007}, isbn = {978-1-4244-1656-1}, pages = {1}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2007.4547601}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - System-in-Package design/testing in memory package SN - 978-1-4244-1656-1 SP EP A1 - Scott Chen, PY - 2007 VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER - | |||
Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions.
Citation:
Scott Chen, "System-in-Package design/testing in memory package," mtdt, pp.1, 2007 IEEE International Workshop on Memory Technology, Design and Testing, 2007
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