Semiconductor Companies are continuously trying to keep their customers Happy and Satisfied with new products, new functionalities and new interfaces. To keep track on inventing products with new more facilities, Semiconductor Companies have to include much more transistors per millimeter square than ever before. Nowadays, System on Chips (SoCs) are very dense, approaching 1 billion of transistors per chip of few millimeters. Interaction of this huge number of transistors in a chip is becoming much more important than few years ago. To be specific, in current process technologies new defects mechanisms and process variation are causing complex faulty behaviours, which are creating new challenges for test experts. Moreover, embedded memories occupy a big portion of SoCs approaching nowadays 70% of total SoC area and are infringing the DFM rules, which creates even higher defect density than logic or analog blocks.

This tutorial will give an overview about high quality memory testing in industrial environment, and how Semiconductor Companies are surviving in competitive markets by delivering high quality products and targeting for Zero Defect escapes for specific customers (e.g., Automotive, Medical Systems, Avionics, etc.). Also, an overview about closing the loop with memory designers and process engineers in early phase of the design is highlighted. Such loop could easily improve the test & yield of embedded memories in short market time window by taking decisive actions on layout level.