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2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)
DDR2 DRAM Output Timing Optimization
Taipei, Taiwan
August 02-August 04
ISBN: 0-7695-2572-5
| ASCII Text | x | ||
| Joerg Vollrath, Juerg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson, "DDR2 DRAM Output Timing Optimization," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 49-54, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06), 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/MTDT.2006.9, author = {Joerg Vollrath and Juerg Schwizer and Marcin Gnat and Ralf Schneider and Bret Johnson}, title = {DDR2 DRAM Output Timing Optimization}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2006}, issn = {1087-4852}, pages = {49-54}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2006.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - DDR2 DRAM Output Timing Optimization SN - 1087-4852 SP49 EP54 A1 - Joerg Vollrath, A1 - Juerg Schwizer, A1 - Marcin Gnat, A1 - Ralf Schneider, A1 - Bret Johnson, PY - 2006 KW - null VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2006.9
The speed of DRAMs is increasing from generation to generation. This paper gives an overview of typical DRAM output timing challenges. Tight output timing specifications in the order of several 100ps are presented. Specification requirements lead to efforts to improve the output driver design. A systematic test strategy evaluates limits of automatic test equipment (ATE) overall timing accuracy (OTA) and device performance. Systematic output timing characterization data leads to guidelines for design improvements. A good characterization strategy gives a feedback to the design of specific weaknesses of output drivers and enables ATEs to test these parameters with high accuracy.
Citation:
Joerg Vollrath, Juerg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson, "DDR2 DRAM Output Timing Optimization," mtdt, pp.49-54, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06), 2006
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