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2003 International Workshop on Memory Technology, Design and Testing (MTDT'03)
San Jose, California
July 28-July 29
ISBN: 0-7695-2004-9
Table of Contents
Introduction
Plenary Session
Program Introduction
MTDT Message
Keynote Address
Platform Architecture and the Persistence of Memory
Session 1: DRAM for Leading Edge Applications
Session 2: Fault Analysis and Test Generation and Verification
Zaid Al-Ars, Delft University of Technology
Said Hamdioui, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
pp. 33
Session 3: Enhanced Testing Techniques
Baosheng Wang, University of British Columbia
Josh Yang, University of British Columbia
Andr? Ivanov, University of British Columbia
pp. 47
Rei-Fu Huang, National Tsing Hua University
Li-Ming Denq, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Jin-Fu Li, National Central University
pp. 53
Session 4: Panel: Are All the Memory BIST Challenges Solved?
Are All the Memory BIST Challenges Solved?
Session 5: Memory Roadmap, Yield and Optimization
M. Choi, University of Missouri-Rolla
N. Park, Oklahoma State University
F. Lombardi, Northeastern University
Y.B. Kim, Northeastern University
V. Piuri, University of Milan
pp. 64
Session 6: Memory Design Techniques
Jean-Michel Daga, ATMEL, Zone Industrielle
Caroline Papaix, ATMEL, Zone Industrielle
Emmanuel Racape, ATMEL, Zone Industrielle
Marylene Combe, ATMEL, Zone Industrielle
Vincent Sialelli, ATMEL, Zone Industrielle
Jeanine Guichaoua, ATMEL, Zone Industrielle
pp. 81
Session 7: Special Session
Panel: Embedded DRAM
Author Index
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