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The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002)
Isle of Bendor, France
July 10-July 12
ISBN: 0-7695-1617-3
Table of Contents
Keynote Address
Embedded Memory Test and Repair
Session B: Memory BIST Analysis and Application
D. Appello, STMicroelectronics
A. Fudoli, STMicroelectronics
V. Tancorre, STMicroelectronics
F. Corno, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
pp. 12
Session C: Memory ECC and Soft Errors
Soft Error Protection for Embedded Memories
Session D: High Reliability in Railway and Automotive Systems
Session E: Embedded Memory Yield Enhancement
Rei-Fu Huang, National Tsing Hua University
Jin-Fu Li, National Tsing Hua University
Jen-Chieh Yeh, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 68
Challenges and Opportunities Created by the SoC Shockwave
Session 1: Embedded Memory Systems and Test Optimization
Robert Gibbins, Nortel Networks
R. Dean Adams, IBM Microelectronics
Thomas Eckenrode, IBM Microelectronics
Michael Ouellette, IBM Microelectronics
Yuejian Wu, Nortel Networks
pp. 83
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process
Session 2: Memory Test Strategies
Said Hamdioui, Intel Corporation and Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Mike Rodgers, Intel Corporation
pp. 95
Session 3: Fault Modeling
Raja Venkatesh, Paxonet Communications
Sailesh Kumar, Paxonet Communications
Joji Philip, Paxonet Communications
Sunil Shukla, Paxonet Communications
pp. 109
Michael Redeker, University of Alberta
Bruce F. Cockburn, University of Alberta
Duncan G. Elliott, University of Alberta
Yunan Xiang, University of Alberta
Sue Ann Ung, University of Alberta
pp. 117
SoC?s Trends and Challenges going to 0.10 ?m
Session 5: EPROM/EEPROM Design
L. Forli, ICF/L2MP-UMR CNRS and ST-Microelectronics
H. Aziza, ICF/L2MP-UMR CNRS and ST-Microelectronics
D. Née, ST-Microelectronics
pp. 137
Session 6: Process Technology and Reliability
T. Devoivre, STMicroelectronics
M. Lunenborg, PHILIPS Semiconductors
C. Julien, STMicroelectronics
J-P. Carrere, STMicroelectronics
P. Ferreira, STMicroelectronics
W. J. Toren, PHILIPS Semiconductors
A. VandeGoor, PHILIPS Semiconductors
P. Gayet, STMicroelectronics
T. Berger, STMicroelectronics
O. Hinsinger, STMicroelectronics
P. Vannier, STMicroelectronics
Y. Rody, PHILIPS Semiconductors
P-J. Goirand, STMicroelectronics
R. Palla, STMicroelectronics
I. Thomas, STMicroelectronics
F. Guyader, STMicroelectronics
D. Roy, STMicroelectronics
B. Borot, STMicroelectronics
N. Planes, STMicroelectronics
S. Naudet, STMicroelectronics
F. Pico, STMicroelectronics
D. Duca, STMicroelectronics
F. Lalanne, STMicroelectronics
D. Heslinga, PHILIPS Semiconductors
M. Haond, STMicroelectronics
pp. 157
R. Laffont, L2MP/Polytech-UMR CNRS and ST-Microelectronics
J. Razafindramora, L2MP/Polytech-UMR CNRS
P. Canet, L2MP/Polytech-UMR CNRS
R. Bouchakour, L2MP/Polytech-UMR CNRS
J. M. Mirabel, ST-Microelectronics
pp. 168
Session 7: Advanced Memory Technologies Panel
Author Index
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