CSDL - Proceedings M

Conference Committee (PDF)

pp. xi

TTTC Information (PDF)

pp. 180

Keynote Address

Embedded Memory Test and Repair

Session B: Memory BIST Analysis and Application

Defect-Oriented Analysis of Memory BIST Tests (Abstract)

Alvin Jee, HPL, Inc.

pp. 7

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A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques (Abstract)

D. Appello, STMicroelectronics

A. Fudoli, STMicroelectronics

V. Tancorre, STMicroelectronics

F. Corno, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

pp. 12

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A Scan-Bist Environment for Testing Embedded Memories (Abstract)

F. Karimi, LTX Corporation

F. Lombardi, Northeastern University

pp. 17

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Session C: Memory ECC and Soft Errors

Soft Error Protection for Embedded Memories

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories (Abstract)

D. Rossi, University of Bologna

C. Metra, University of Bologna

B. Riccò, University of Bologna

pp. 27

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High Speed 15 ns 4 Mbits SRAM for Space Application (Abstract)

Bernard Coloma, Atmel Corporation

Patrick Delaunay, Atmel Corporation

Olivier Husson, Atmel Corporation

pp. 32

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Session D: High Reliability in Railway and Automotive Systems

The YATE Fail-Safe Interface: The User?s Point of View (Abstract)

D. BIED-CHARRETON, INRETS

D. GUILLON, TECHNICATOME

B. JACQUES, CSEE Transport

pp. 39

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Fault Tolerant Insertion and Verification: A Case Study (Abstract)

Alberto Manzone, Centro Ricerche FIAT

Diego De Costantini, Centro Ricerche FIAT

pp. 44

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Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems (Abstract)

Luca Schiano, University of Bologna

Cecilia Metra, University of Bologna

Diego Marino, Alstom Transport Spa

pp. 49

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Session E: Embedded Memory Yield Enhancement

A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios (Abstract)

Emmanuel Rondey, Altis Semiconductor

Yann Tellier, Infineon Technologies

Simone Borri, Infineon Technologies

pp. 57

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A March-Based Fault Location Algorithm for Static Random Access Memories (Abstract)

Valery A. Vardanian, Virage Logic Int.

Yervant Zorian, Virage Logic

pp. 62

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A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories (Abstract)

Rei-Fu Huang, National Tsing Hua University

Jin-Fu Li, National Tsing Hua University

Jen-Chieh Yeh, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 68

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Challenges and Opportunities Created by the SoC Shockwave

Session 1: Embedded Memory Systems and Test Optimization

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch (Abstract)

Robert Gibbins, Nortel Networks

R. Dean Adams, IBM Microelectronics

Thomas Eckenrode, IBM Microelectronics

Michael Ouellette, IBM Microelectronics

Yuejian Wu, Nortel Networks

pp. 83

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Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process

Adder Merged DRAM Architecture (Abstract)

Masashi Hashimoto, Cadence Design Systems

pp. 88

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Session 2: Memory Test Strategies

March SS: A Test for All Static Simple RAM Faults (Abstract)

Said Hamdioui, Intel Corporation and Delft University of Technology

Ad J. van de Goor, Delft University of Technology

Mike Rodgers, Intel Corporation

pp. 95

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Random Testing of Multi-Port Static Random Access Memories (Abstract)

F. Karimi, LTX Corporation

F. J. Meyer, Northeastern University

F. Lombardi, Northeastern University

pp. 101

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Session 3: Fault Modeling

A Fault Modeling Technique to Test Memory BIST Algorithms (Abstract)

Raja Venkatesh, Paxonet Communications

Sailesh Kumar, Paxonet Communications

Joji Philip, Paxonet Communications

Sunil Shukla, Paxonet Communications

pp. 109

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Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM (Abstract)

Michael Redeker, University of Alberta

Bruce F. Cockburn, University of Alberta

Duncan G. Elliott, University of Alberta

Yunan Xiang, University of Alberta

Sue Ann Ung, University of Alberta

pp. 117

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An Investigation into Crosstalk Noise in DRAM Structures (Abstract)

Michael Redeker, University of Hanover

Bruce F. Cockburn, University of Alberta

Duncan G. Elliott, University of Alberta

pp. 123

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SoC?s Trends and Challenges going to 0.10 ?m

Session 5: EPROM/EEPROM Design

An Automated Design Methodology for EEPROM Cell (ADE) (Abstract)

J. M. Portal, ICF/L2MP-UMR CNRS

L. Forli, ICF/L2MP-UMR CNRS and ST-Microelectronics

H. Aziza, ICF/L2MP-UMR CNRS and ST-Microelectronics

D. Née, ST-Microelectronics

pp. 137

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A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology (Abstract)

Cyrille Dray, STMicroelectronics

Philippe Gendrier, STMicroelectronics

pp. 143

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A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories (Abstract)

Caroline Papaix, ATMEL ROUSSET and Montpellier University

Jean Michel Daga, ATMEL ROUSSET

pp. 149

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Session 6: Process Technology and Reliability

Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) (Abstract)

T. Devoivre, STMicroelectronics

M. Lunenborg, PHILIPS Semiconductors

C. Julien, STMicroelectronics

J-P. Carrere, STMicroelectronics

P. Ferreira, STMicroelectronics

W. J. Toren, PHILIPS Semiconductors

A. VandeGoor, PHILIPS Semiconductors

P. Gayet, STMicroelectronics

T. Berger, STMicroelectronics

O. Hinsinger, STMicroelectronics

P. Vannier, STMicroelectronics

Y. Trouiller, LETI

Y. Rody, PHILIPS Semiconductors

P-J. Goirand, STMicroelectronics

R. Palla, STMicroelectronics

I. Thomas, STMicroelectronics

F. Guyader, STMicroelectronics

D. Roy, STMicroelectronics

B. Borot, STMicroelectronics

N. Planes, STMicroelectronics

S. Naudet, STMicroelectronics

F. Pico, STMicroelectronics

D. Duca, STMicroelectronics

F. Lalanne, STMicroelectronics

D. Heslinga, PHILIPS Semiconductors

M. Haond, STMicroelectronics

pp. 157

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Converting an Embedded Low-Power SRAM from Bulk to PD-SOI (Abstract)

Mario R. Casu, Politecnico di Torino

Philippe Flatresse, ST Microelectronics

pp. 163

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Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact (Abstract)

R. Laffont, L2MP/Polytech-UMR CNRS and ST-Microelectronics

J. Razafindramora, L2MP/Polytech-UMR CNRS

P. Canet, L2MP/Polytech-UMR CNRS

R. Bouchakour, L2MP/Polytech-UMR CNRS

J. M. Mirabel, ST-Microelectronics

pp. 168

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Session 7: Advanced Memory Technologies Panel

Panel on Advanced Embedded Memory Technologies (PDF)

Bruce F. Cockburn, University of Alberta

pp. 177

Author Index

Author Index (PDF)

pp. 179