CSDL - Proceedings M

Conference Committee (PDF)

pp. viii

TTTC Information (PDF)

pp. 106

Session 1: Memory Design

A DRAM Compiler for Fully Optimized Memory Instances (Abstract)

G. Harling

pp. 0003

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Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme (Abstract)

Kyung-Saeng Kim, Korea Advanced Institute of Science and Technology (KAIST)

KwangMyoung Rho, Korea Advanced Institute of Science and Technology (KAIST)

Kwyro Lee, Korea Advanced Institute of Science and Technology (KAIST)

pp. 0009

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Design of an Embedded Fully-Depleted SOI SRAM (Abstract)

Raymond J. Sung, University of Alberta

John C. Koob, University of Alberta

Tyler L. Brandon, University of Alberta

Duncan G. Elliott, University of Alberta

Bruce F. Cockburn, University of Alberta

pp. 0013

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Session 2: Memory BIST

A P1500 Compliant Programable BistShell for Embedded Memories (Abstract)

Sandeep Koranne, ED&T/Test

Tom Waayers, ED&T/Test

Robert Beurze, ED&T/Test

Clemens Wouters, AMDC

Sunil Kumar, Philips Semiconductors

G. S. Visweswaran, IIT-Delhi

pp. 0021

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BIST-Based Bitfail Mapping of an Embedded DRAM (Abstract)

Brian R. Kessler, International Business Machines Corp.

Jeffrey Dreibelbis, International Business Machines Corp.

Tim McMahon, International Business Machines Corp.

Joshua S. McCloy, International Business Machines Corp.

Rex Kho, International Business Machines Corp.

pp. 0029

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Session 5: Redundancy and Error Control

A Method to Caculate Redundancy Coverage for FLASH Memory (Abstract)

S. Matarrese, STMicroelectronics

L. Fasoli, STMicroelectronics

pp. 0041

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An Error Control Code Scheme for Multilevel Flash Memories (Abstract)

Stefano Gregori, University of Pavia

Guido Torelli, University of Pavia

Osama Khouri, STMicroelectronics

Rino Micheloni, STMicroelectronics

pp. 0045

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An Approach for Evaluation of Redunancy Analysis Algorithms (Abstract)

S. Shoukourian, Virage Logic Int.

V. Vardanian, Virage Logic Int.

Y. Zorian, Virage Logic Corp.

pp. 0051

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Session 6: Fault Models and Multi-Port SRAM Testing

Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests (Abstract)

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

pp. 0059

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Realistic Fault Models and Test Procedures for Multi-Port SRAMs (Abstract)

Said Hamdioui, Intel Corporation

Ad J. van de Goor, Delft University of Technology

David Eastwick, Intel Corporation

Mike Rodgers, Intel Corporation

pp. 0065

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A Parallel Approach for Testing Multi-Port Static Random Access Memories (Abstract)

F. Karimi, Northeastern University

F. Lombardi, Northeastern University

S. Irrinki, LSI Logic Inc.

T. Crosby, LSI Logic Inc.

pp. 0073

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Session 7: Verification and Test

Equivalence Checking a 256MB SDRAM (Abstract)

Simon Napper, InnoLogic Systems Inc.

Dian Yang, InnoLogic Systems Inc.

pp. 0085

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Testing Carry Logic Modules of SRAM-based FPGAs (Abstract)

Xiaoling Sun, University of Alberta

Jian Xu, University of Alberta

Pieter Trouborst, Nortel Networks

pp. 0091

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Low Output Resistance Charge Pump for Flash Memory Programming (Abstract)

Osama Khouri, STMicroelectronics

Stefano Gregori, University of Pavia

Dario Soltesz, University of Pavia

Guido Torelli, University of Pavia

Rino Micheloni, STMicroelectronics

pp. 0099

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Author Index (PDF)

pp. 0105