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International Workshop on Memory Technology, Design, and Testing (MTDT'01)
San Jose, California
August 06-August 07
ISBN: 0-7695-1242-9
Table of Contents
Session 1: Memory Design
Kyung-Saeng Kim, Korea Advanced Institute of Science and Technology (KAIST)
KwangMyoung Rho, Korea Advanced Institute of Science and Technology (KAIST)
Kwyro Lee, Korea Advanced Institute of Science and Technology (KAIST)
pp. 0009
Raymond J. Sung, University of Alberta
John C. Koob, University of Alberta
Tyler L. Brandon, University of Alberta
Duncan G. Elliott, University of Alberta
Bruce F. Cockburn, University of Alberta
pp. 0013
Session 2: Memory BIST
Brian R. Kessler, International Business Machines Corp.
Jeffrey Dreibelbis, International Business Machines Corp.
Tim McMahon, International Business Machines Corp.
Joshua S. McCloy, International Business Machines Corp.
Rex Kho, International Business Machines Corp.
pp. 0029
Session 5: Redundancy and Error Control
Session 6: Fault Models and Multi-Port SRAM Testing
Said Hamdioui, Intel Corporation
Ad J. van de Goor, Delft University of Technology
David Eastwick, Intel Corporation
Mike Rodgers, Intel Corporation
pp. 0065
Session 7: Verification and Test
Simon Napper, InnoLogic Systems Inc.
Dian Yang, InnoLogic Systems Inc.
pp. 0085
Osama Khouri, STMicroelectronics
Stefano Gregori, University of Pavia
Dario Soltesz, University of Pavia
Guido Torelli, University of Pavia
Rino Micheloni, STMicroelectronics
pp. 0099
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