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Memory Technology, Design and Testin, IEEE International Workshop on (2001)
San Jose, California
Aug. 6, 2001 to Aug. 7, 2001
ISBN: 0-7695-1242-9
pp. 106
Session 1: Memory Design
KwangMyoung Rho , Korea Advanced Institute of Science and Technology (KAIST)
Kyung-Saeng Kim , Korea Advanced Institute of Science and Technology (KAIST)
pp. 0009
Raymond J. Sung , University of Alberta
John C. Koob , University of Alberta
Tyler L. Brandon , University of Alberta
Duncan G. Elliott , University of Alberta
Bruce F. Cockburn , University of Alberta
pp. 0013
Session 2: Memory BIST
Tom Waayers , ED&T/Test
Robert Beurze , ED&T/Test
Sunil Kumar , Philips Semiconductors
G. S. Visweswaran , IIT-Delhi
pp. 0021
Brian R. Kessler , International Business Machines Corp.
Jeffrey Dreibelbis , International Business Machines Corp.
Tim McMahon , International Business Machines Corp.
Joshua S. McCloy , International Business Machines Corp.
Rex Kho , International Business Machines Corp.
pp. 0029
Session 5: Redundancy and Error Control
S. Matarrese , STMicroelectronics
L. Fasoli , STMicroelectronics
pp. 0041
Guido Torelli , University of Pavia
Osama Khouri , STMicroelectronics
Stefano Gregori , University of Pavia
pp. 0045
V. Vardanian , Virage Logic Int.
S. Shoukourian , Virage Logic Int.
pp. 0051
Session 6: Fault Models and Multi-Port SRAM Testing
Zaid Al-Ars , Delft University of Technology
pp. 0059
Ad J. van de Goor , Delft University of Technology
David Eastwick , Intel Corporation
Mike Rodgers , Intel Corporation
pp. 0065
F. Lombardi , Northeastern University
F. Karimi , Northeastern University
T. Crosby , LSI Logic Inc.
pp. 0073
Session 7: Verification and Test
Simon Napper , InnoLogic Systems Inc.
Dian Yang , InnoLogic Systems Inc.
pp. 0085
Jian Xu , University of Alberta
Xiaoling Sun , University of Alberta
pp. 0091
Osama Khouri , STMicroelectronics
Stefano Gregori , University of Pavia
Dario Soltesz , University of Pavia
Guido Torelli , University of Pavia
Rino Micheloni , STMicroelectronics
pp. 0099
Author Index (PDF)
pp. 0105
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