Message from the General Chair

Message from the Technical Program Chair (PDF)

pp. ix

Conference Committee (PDF)

pp. x

Plenary Session

Welcome Message

Program Introduction

Session 1: Failure Mechanism/Defects: Chair: Betty Prince, Memory Strategy International

Failure Mechanisms in Semiconductor Memory Circuits (Abstract)

Ray Haythornthwaite, Chipworks Inc

pp. 7

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Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models (Abstract)

Jun Zhao, Texas A&M University

Fred J. Meyer, Northeastern University

Fabrizio Lombardi, Northeastern University

pp. 14

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Optimizing Memory Tests by Analyzing Defect Coverage (Abstract)

Alvin Jee, HPL, Inc.

Jonathon E. Colburn, HPL, Inc.

V. Swamy Irrinki, LSI Logic

Mukesh Puri, LSI Logic

pp. 20

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Session 2: Flash/EEPROM Design: Chair: Alex Shubat, Virage Logic

Hierarchical Sector Biasing Organization for Flash Memories (Abstract)

Rino Micheloni, STMicroelectronics

Matteo Zammattio, STMicroelectronics

Giovanni Campardo, STMicroelectronics

Osama Khouri, University of Pavia

Guido Torelli, University of Pavia

pp. 29

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Fast Voltage Regulator for Multilevel Flash Memories (Abstract)

Osama Khouri, STMicroelectronics and University of Pavia

Rino Micheloni, STMicroelectronics

Stefano Gregori, University of Pavia

Guido Torelli, University of Pavia

pp. 34

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Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions (Abstract)

Jean Michel Daga, ATMEL ROUSSETRANCE

Caroline Papaix, ATMEL ROUSSETRANCE

Marc Merandat, ATMEL ROUSSETRANCE

Stephane Ricard, ATMEL ROUSSETRANCE

Giuseppe Medulla, ATMEL ROUSSETRANCE

Jeanine Guichaoua, ATMEL ROUSSETRANCE

Daniel Auvergne, Montpellier II University

pp. 39

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Session 3: New Ideas: Chair: Fabrizio Lombardi, Northeastern University

Windowed MRAM Sensing Scheme (Abstract)

Ruili Zhang, Texas Instruments

William C. Black Jr, Iowa State University

Marwan M. Hassoun, Iowa State University

pp. 47

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Session 4

Future Memory Challenges

Session 5: Test and Yield: Chair: Robert Evans, Mosaid

Synchronous Dynamic Memory Test Construction: A Field Approach (Abstract)

Joerg Vollrath, White Oak Semiconductor

pp. 59

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Yield Analysis Methodology for Low Defectivity Wafer Fabs (Abstract)

Kamal Rajkanan, KLA-Tencor Corporation

pp. 65

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Session 6: Memory Testing and Built-in Self-Test: Chair: Swamy Irrinki, LSI Logic

March Tests for Realistic Faults in Two-Port Memories (Abstract)

Said Hamdioui, Delft University of Technology and Intel Corporation

Ad J. van de Goor, Delft University of Technology

Mike Rodgers, Intel Corporation

David Eastwick, Intel Corporation

pp. 73

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A Simple Built-In Self Test For Dual Ported SRAMs (Abstract)

Khoan Truong, Cadence Design Systems, Inc.

pp. 79

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Using GLFSRs for Pseudo-Random Memory BIST (Abstract)

Michael Redeker, University of Hannover

Markus Rudack, University of Hannover

Thomas Lobbe, University of Hannover

Dirk Niggemeyer, University of Illinois at Urbana-Champaign

pp. 85

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Invited Address

1-T Sram

Session 7: Memory Design: Chair: Robert Gibbins, Nortel

Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems (Abstract)

Wen-Tsong Shiue, Arizona State University

pp. 95

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66MHz 2.3M Ternary Dynamic Content Addressable Memory (Abstract)

Valerie Lines, Mosaid Technologies Incorporated

Abdullah Ahmed, Mosaid Technologies Incorporated

Peter Ma, Mosaid Technologies Incorporated

Stanley Ma, Mosaid Technologies Incorporated

Robert McKenzie, Mosaid Technologies Incorporated

Hong-Seok Kim, Mosaid Technologies Incorporated

Cynthia Mar, Mosaid Technologies Incorporated

pp. 101

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A Low Voltage Embedded Single Port SRAM Generator in a 0.18?m Standard CMOS Process (Abstract)

C. Frey, ST Microelectronics

F. Genevaux, ST Microelectronics

C. Issartel, ST Microelectronics

D. Turgis, ST Microelectronics

Jp. Schoellkopf, ST Microelectronics

pp. 106

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Session 8: Diagnosis: Chair: Sharon Murray, Medtronic Micro-Rel

Diagnostic Testing of Embedded Memories Based on Output Tracing (Abstract)

Dirk Niggemeyer, University of Illinois at Urbana-Champaign

Elizabeth M. Rudnick, University of Illinois at Urbana-Champaign

Michael Redeker, University of Hannover

pp. 113

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Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories (Abstract)

Kamran Zarrineh, IBM Microelectronics

R. Dean Adams, IBM Microelectronics

Aneesha P . Deo, State University of New York at Buffalo

pp. 119

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Crosstalk in Deep Submicron DRAMs (Abstract)

Zemo Yang, Santa Clara University

Samiha Mourad, Santa Clara University

pp. 125

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Author Index (PDF)

pp. 131