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1999
1999 IEEE International Workshop on Memory Technology, Design, and Testing
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Bibliographic References
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Refworks Procite/RefMan
1999 IEEE International Workshop on Memory Technology, Design, and Testing
San Jose, California
August 09-August 10
ISBN: 0-7695-0259-8
Table of Contents
Message from the General Chair
(PDF)
pp. vii
ABSTRACT
PDF
Message from the Technical Program Chair
(PDF)
pp. viii
ABSTRACT
PDF
Conference Committee
(PDF)
pp. ix
ABSTRACT
PDF
Keynote Address
Session I: Tutorial on Low Power SRAMs
Low Power SRAMs for Battery Operation
(PDF)
Martin Margala
, University of Alberta
pp. 6
ABSTRACT
PDF
Session II: Architecture and Applications
Computing in Memory Architectures for Digital Image Processing
(Abstract)
Luke Roth Lee Coraor
, Pennsylvania State University
David Landis
, Pennsylvania State University
Paul Hulina
, Pennsylvania State University
Scott Deno
, Pennsylvania State University
pp. 8
ABSTRACT
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Unbalanced Cache Systems
(Abstract)
David L. Rhodes
, United States Army and Princeton University
Wayne Wolf
, Princeton University
pp. 16
ABSTRACT
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The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval
(Abstract)
G. Lipovski
C. Yu
pp. 24
ABSTRACT
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Session III: Diagnosis and Yield
Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis
(Abstract)
Sue Brown
, Chipworks Incorporated
Jeff Campbell
, Chipworks Incorporated
Sherri Griffin
, Chipworks Incorporated
Dick James
, Chipworks Incorporated
Ray Haythornthwaite
, Chipworks Incorporated
pp. 34
ABSTRACT
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Interconnect Diagnosis of Bus-Connected Multi-RAM Systems _
(Abstract)
Jun Zhao
, Texas A&M University
Fred J. Meyer
, Northeastern University
Fabrizio Lombardi
, Northeastern University
pp. 40
ABSTRACT
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Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis
(Abstract)
Hpl Inc.
pp. 48
ABSTRACT
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Design Validation of .18 um 1 Ghz Cache and Register Arrays
(Abstract)
Doug Malone
, IBM Corp.
pp. 54
ABSTRACT
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Session IV: Tutorial on SDRAMs
Tutorial: Characterizing SDRAMS
(Abstract)
Joerg Vollrath
, White Oak Semiconductor
pp. 62
ABSTRACT
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Session V: Memory Testing topics
Built In Self Test for Ring Addressed FIFOs with Transparent Latches
(Abstract)
Larry Fenstermaker
, Lucent Technologies
Ilyoung Kim
, Lucent Technologies
Jim Lewandowski
, Lucent Technologies
Jeffrey J. Nagy
, Lucent Technologies
pp. 72
ABSTRACT
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A Fast Test to Generate Flash Memory Threshold Voltage Distribution Map
(Abstract)
Raju Khubchandani
, MOSAID Technologies, Inc.
pp. 78
ABSTRACT
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Modeling and Testing Transistor Faults in Content-Addressable Memories
(Abstract)
Piotr R. Sidorowicz
, University of Waterloo
pp. 83
ABSTRACT
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Designing a Memory Module Tester
(Abstract)
Daniel P. Van der Velde
, Delft University of Technology
A.J. v.d. Goor
, Delft University of Technology
pp. 91
ABSTRACT
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Session VI: Special Session
Panel on Memories, IP and System-on-a-Chip
Session VII: New Ideas in Technology and Design
A Comparative Simulation Study of Four Multilevel DRAMs
(Abstract)
Gershom Birk
, University of Alberta
Duncan G. Elliott
, University of Alberta
Bruce F. Cockburn
, University of Alberta
pp. 102
ABSTRACT
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The Potential of Carbon-Based Memory Systems
(Abstract)
Mark Brehob
, Michigan State University
Richard Enbody
, Michigan State University
pp. 110
ABSTRACT
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Low-Power SRAM Circuit Design
(Abstract)
Martin Margala
, University of Alberta
pp. 115
ABSTRACT
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A Tribute to Graphics Drams
(Abstract)
Betty Prince
, Memory Strategies International
pp. 123
ABSTRACT
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Author Index
(PDF)
pp. 131
ABSTRACT
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