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Memory Technology, Design and Testin, IEEE International Workshop on (1998)
San Jose, California
Aug. 24, 1998 to Aug. 25, 1998
ISBN: 0-8186-8494-1
TABLE OF CONTENTS
pp. vii
Session 1: Embedded Memory Design Aids
Session 2: Embedded DRAM
Y-H. Wong , LUCENT Corporation
C-T Liu , LUCENT Corporation
K-H. Lee , LUCENT Corporation
R. Dail , LUCENT Corporation
W.S. Lindenberger , LUCENT Corporation
A.C.. Dumbri , LUCENT Corporation
M.V. Depaolis , LUCENT Corporation
J.T. Clemens , LUCENT Corporation
W.W. Troutman , LUCENT Corporation
K. Noda , NEC Corporation
J.M. Drynan , NEC Corporation
M. Nakamae , NEC Corporation
pp. 24
M. Karpovsky , Boston University
L. Zakrevski , Boston University
pp. 31
Session 3: Algorithms and Testing Techniques
L. Fenstermaker , Lucent Technologies, Bell Labs
F. Higgins , Lucent Technologies, Bell Labs
I. Kim , Lucent Technologies, Bell Labs
J. Lewandowski , Lucent Technologies, Bell Labs
J. Nagy , Lucent Technologies, Bell Labs
pp. 53
Jian Liu , Fujitsu Microelectronics, Inc.
pp. 57
Tutorial: DRAM Fault Modeling
Tutorial: SRAM Characterization and Test
Session 4: CAM Testing
Session 5: Unique Fault Models
Bruce F. Cockburn , University of Alberta
Duncan G. Elliott , University of Alberta
pp. 84
T. Monnier , Universit? Montpellier II / CNRS
F.M. Roche , Universit? Montpellier II / CNRS
G. Cathébras , Universit? Montpellier II / CNRS
pp. 104
Session 6: Memory Repair
Gianluca Battaglini , University of Rome La Sapienza
Bruno Ciciani , University of Rome La Sapienza
pp. 117
Author Index (PDF)
pp. 131
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