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  • 1997 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '97)
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1997 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '97)
San Jose, CA
August 11-August 12
ISBN: 0-8186-8099-7
Table of Contents
Keynote Address
Architectures
A. Glaser, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Nakkar, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
P. Franzon, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
G. Rinne, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Roberson, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
V. Rogers, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
C.K. Williams, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 2
V. Lines, MOSAID Technol. Inc., Canada
M. Abou-Seido, MOSAID Technol. Inc., Canada
C. Mar, MOSAID Technol. Inc., Canada
A. Achyuthan, MOSAID Technol. Inc., Canada
S. Miyamoto, MOSAID Technol. Inc., Canada
Y. Murashima, MOSAID Technol. Inc., Canada
S. Sakuma, MOSAID Technol. Inc., Canada
pp. 8
Fault Modeling and Manufacturing
A.J. van de Goor, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G.N. Gaydadjiev, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 13
Von-Kyoung Kim, Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
T. Chen, Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
pp. 21
R.D. Adams, Dartmouth's Thayer Sch. of Eng., Hanover, NH, USA
E.S. Cooley, Dartmouth's Thayer Sch. of Eng., Hanover, NH, USA
pp. 27
D. Niggemeyer, Lab. fur Informationstechnol., Hannover Univ., Germany
J. Otterstedt, Lab. fur Informationstechnol., Hannover Univ., Germany
M. Redeker, Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 33
Tools
M. Pandey, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Bryant, Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 42
S.U. Hegde, Texas Instrum. (India) Ltd., Bangalore, India
I.P. Pal, Texas Instrum. (India) Ltd., Bangalore, India
K.S. Rao, Texas Instrum. (India) Ltd., Bangalore, India
pp. 50
Low Power
R. Kanan, Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
M. Declercq, Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
A. Guyot, Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
B. Hochet, Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 58
C.A. Zukowski, Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Shao-Yi Wang, Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 64
Test
A. Offerman, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van de Goor, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 71
W.K. Huang, Dept. of Electr. Eng., Fudan Univ., Shanghai, China
F.J. Meyer, Dept. of Electr. Eng., Fudan Univ., Shanghai, China
N. Park, Dept. of Electr. Eng., Fudan Univ., Shanghai, China
F. Lombardi, Dept. of Electr. Eng., Fudan Univ., Shanghai, China
pp. 79
S. Yano, 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
N. Ishiura, 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
pp. 87
Sensing
C. Calligaro, Dipt. di Elettronica, Pavia Univ., Italy
R. Gastaldi, Dipt. di Elettronica, Pavia Univ., Italy
A. Manstretta, Dipt. di Elettronica, Pavia Univ., Italy
G. Torelli, Dipt. di Elettronica, Pavia Univ., Italy
pp. 96
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