San Jose, CA
Aug. 11, 1997 to Aug. 12, 1997
Von-Kyoung Kim , Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
T. Chen , Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
This paper describes an early memory yield prediction model using a memory sensitive area model. The proposed sensitive area prediction model calculates the sensitive area of a memory block for a given process technology and memory capacity. The model is capable of predicting the yield of a memory block in the early design phase without the derailed knowledge of the physical layout. The use of such a model in the early design stage helps to improve product quality and to reduce cost.
SRAM chips; SRAM yield estimation; design cycle; early memory yield prediction model; memory sensitive area model; physical layout; IC design
Von-Kyoung Kim, T. Chen, "SRAM yield estimation in the early stage of the design cycle", MTDT, 1997, Memory Technology, Design and Testin, IEEE International Workshop on, Memory Technology, Design and Testin, IEEE International Workshop on 1997, pp. 21, doi:10.1109/MTDT.1997.619390