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Memory Technology, Design and Testin, IEEE International Workshop on (1995)
San Jose, California
Aug. 7, 1995 to Aug. 8, 1995
ISBN: 0-8186-7102-5
TABLE OF CONTENTS
pp. ix
Keynote Speech
B. Prince , Meomory Strategies Int., Sugarland, TX, USA
pp. 2
Session 1: Role of Simulation in Memory Design: Chairs: David Lepejian, HPL, USA
D.V. Das , Cadence Design Syst. Pvt. Ltd., Noida, India
M. Lauria , Cadence Design Syst. Pvt. Ltd., Noida, India
pp. 10
X.C. Gao , Cadence Design Syst. Inc., San Jose, CA, USA
R. Hamazaki , Cadence Design Syst. Inc., San Jose, CA, USA
H. Kikuchi , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 15
V. Daniele , Dipartimento di Elettronica, Pavia Univ., Italy
R. Gastaldi , Dipartimento di Elettronica, Pavia Univ., Italy
A. Manstretta , Dipartimento di Elettronica, Pavia Univ., Italy
G. Torelli , Dipartimento di Elettronica, Pavia Univ., Italy
pp. 21
Session 2: Tutorial: Testing Random Access Memories: Chair: Bernard Courtois, INPGITIMA, France
M. Franklin , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K.K. Saluja , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 29
Session 3: Bridging Faults and IDDQ Testing: Chairs: Y.S. Khim, Texas Instruments, Singapore
W.K. Al-Assadi , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Y.K. Malaiya , Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 36
M. Hashizume , Fac. of Eng., Tokushima Univ., Japan
K. Taga , Fac. of Eng., Tokushima Univ., Japan
T. Koyama , Fac. of Eng., Tokushima Univ., Japan
T. Tamesada , Fac. of Eng., Tokushima Univ., Japan
pp. 42
S.M. Menon , Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
A. Nymoen , Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
pp. 48
Session 4: Memory Built-In Self-Test: Chairs: Yervant Zorian, AT&T Bell Labs, USA
A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 56
T. Matsumura , NTT Network Service Syst. Labs., Tokyo, Japan
pp. 62
G.F.R. Gibson , Northern Telecom, Ottawa, Ont., Canada
S.M.I. Adham , Northern Telecom, Ottawa, Ont., Canada
B. Nadeau-Dostie , Northern Telecom, Ottawa, Ont., Canada
pp. 68
Session 5: Application Specific Memory Designs: Chairs: Abhaya Asthana, AT&T Bell Labs, USA
G.M. Lattimore , STA Div., IBM Corp., Austin, TX, USA
M. Kumar , STA Div., IBM Corp., Austin, TX, USA
J.M. Poplawski, Jr. , STA Div., IBM Corp., Austin, TX, USA
pp. 76
F. Catthoor , IMEC, Leuven, Belgium
F. Balasa , IMEC, Leuven, Belgium
F. Franssen , IMEC, Leuven, Belgium
E. De Greef , IMEC, Leuven, Belgium
L. Nachtergaele , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 82
S. Van Singel , Electron. Div., Ford Motor Co., Dearborn, MI, USA
N. Soparkar , Electron. Div., Ford Motor Co., Dearborn, MI, USA
pp. 88
Session 6: Advance Memory Architectures: Chairs: A.J. van de Goor, Delft University of Technology, The Netherlands
J.A. Gasbarro , Rambus Inc., USA
pp. 94
T. Tabe , Electron. Div., Ford Motor Co., Dearborn, MI, USA
N. Soparkar , Electron. Div., Ford Motor Co., Dearborn, MI, USA
S. Van Singel , Electron. Div., Ford Motor Co., Dearborn, MI, USA
pp. 97
K. Eshraghian , Centre for Appl. Microelectron., Univ. of Las Palmas, Gran Canaria, Spain
M.K. McGeever , Centre for Appl. Microelectron., Univ. of Las Palmas, Gran Canaria, Spain
A. Nunez , Centre for Appl. Microelectron., Univ. of Las Palmas, Gran Canaria, Spain
R. Sarmiento , Centre for Appl. Microelectron., Univ. of Las Palmas, Gran Canaria, Spain
pp. 103
Session 7: New Topics in Memory Testing: Chairs: R. Gibons, Northern Telecom, Canada
W.B. Noghani , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
pp. 110
B.F. Cockburn , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 117
J.A. Brzozowski , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
pp. 123
Author Index (PDF)
pp. 129
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