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2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)
2007 IEEE International Conference on Microelectronic Systems Education (MSE'07) 2007 (vol. 0 no. 0)
pp. 37-38
ASCII Text
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Ezequiel Herruzo, J. Ignacio Benavides, Ricardo Quislant, Emilio L. Zapata, Oscar Plata, "Simulating a Reconfigurable Cache System for Teaching Purposes," Microelectronics Systems Education, IEEE International Conference on, vol. 0, no. 0, pp. 37-38, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), 2007.
 
 
BibTex
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@article{ 10.1109/MSE.2007.74,
author = {Ezequiel Herruzo and J. Ignacio Benavides and Ricardo Quislant and Emilio L. Zapata and Oscar Plata},
title = {Simulating a Reconfigurable Cache System for Teaching Purposes},
journal ={Microelectronics Systems Education, IEEE International Conference on},
volume = {0},
year = {2007},
doi = {http://doi.ieeecomputersociety.org/10.1109/MSE.2007.74},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Microelectronics Systems Education, IEEE International Conference on
TI - Simulating a Reconfigurable Cache System for Teaching Purposes
SP37
EP38
A1 - Ezequiel Herruzo,
A1 - J. Ignacio Benavides,
A1 - Ricardo Quislant,
A1 - Emilio L. Zapata,
A1 - Oscar Plata,
PY - 2007
KW - null
VL - 0
JA - Microelectronics Systems Education, IEEE International Conference on
ER -
 
Ezequiel Herruzo, University of Cordoba, Spain
J. Ignacio Benavides, University of Cordoba, Spain
Ricardo Quislant, University of Malaga, Spain
Emilio L. Zapata, University of Malaga, Spain
Oscar Plata, University of Malaga, Spain
This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the ISA level. The tool was developed through a series of laboratory exercises in Computer Architecture. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of C, W and L (cache capacity, block size and number of blocks per set) without changing its architecture. The students are introduced to reconfigurable hardware architecture while refreshing their knowledge on Computer Architecture issues like Digital Design, Register Transfer Level and Computer System Level.
Citation:
Ezequiel Herruzo, J. Ignacio Benavides, Ricardo Quislant, Emilio L. Zapata, Oscar Plata, "Simulating a Reconfigurable Cache System for Teaching Purposes," Microelectronics Systems Education, IEEE International Conference on, vol. 0, no. 0, pp. 37-38, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07) 2007, doi:10.1109/MSE.2007.74
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