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2003 International Conference on Microelectronics Systems Education (MSE'03)
2003 International Conference on Microelectronics Systems Education (MSE'03) 2003 (vol. 0 no. 0)
pp. 134
ASCII Text
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J. E. Becker, C. Bieser, A. Thomas, K. D. M?ller-Glaser, J. Becker, "Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core," Microelectronics Systems Education, IEEE International Conference on, vol. 0, no. 0, pp. 134, 2003 International Conference on Microelectronics Systems Education (MSE'03), 2003.
 
 
BibTex
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@article{ 10.1109/MSE.2003.1205288,
author = {J. E. Becker and C. Bieser and A. Thomas and K. D. M?ller-Glaser and J. Becker},
title = {Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core},
journal ={Microelectronics Systems Education, IEEE International Conference on},
volume = {0},
year = {2003},
doi = {http://doi.ieeecomputersociety.org/10.1109/MSE.2003.1205288},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Microelectronics Systems Education, IEEE International Conference on
TI - Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core
SP
EP
A1 - J. E. Becker,
A1 - C. Bieser,
A1 - A. Thomas,
A1 - K. D. M?ller-Glaser,
A1 - J. Becker,
PY - 2003
KW - null
VL - 0
JA - Microelectronics Systems Education, IEEE International Conference on
ER -
 
J. E. Becker, Universit?t Karlsruhe
C. Bieser, Universit?t Karlsruhe
A. Thomas, Universit?t Karlsruhe
K. D. M?ller-Glaser, Universit?t Karlsruhe
J. Becker, Universit?t Karlsruhe
This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills of today?s engineers. An engineer?s view must no longer be restricted to his/her own work, but has to be widened to a complete system view.
To provide an appropriate education scheme the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. Its goal is to improve students skills not only in a single direction, but to deliver an efficient inter disciplinary hardware/software lab course, combined with training state-of-the-art industrial architectures and relevant tools.
Citation:
J. E. Becker, C. Bieser, A. Thomas, K. D. M?ller-Glaser, J. Becker, "Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core," Microelectronics Systems Education, IEEE International Conference on, vol. 0, no. 0, pp. 134, 2003 International Conference on Microelectronics Systems Education (MSE'03) 2003, doi:10.1109/MSE.2003.1205288
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