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MICRO
2007
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
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40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Chicago, Illinois, USA
December 01-December 05
ISBN: 0-7695-3047-8
Table of Contents
Session 1: Technology Issues
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
(Abstract)
R. Balasubramonian
, Univ. of Utah, Salt Lake City
N. Muralimanohar
, Univ. of Utah, Salt Lake City
N. Jouppi
pp. 3-14
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Introduction
list-reviewer
(PDF)
pp. xi
ABSTRACT
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Message from the General Chairs
(PDF)
pp. viii
ABSTRACT
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Message from the Program Chairs
(PDF)
pp. ix
ABSTRACT
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Organizing Committee
(PDF)
pp. x
ABSTRACT
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Process Variation Tolerant 3T1D-Based Cache Architectures
(Abstract)
Xiaoyao Liang
Ramon Canal
Gu-Yeon Wei
David Brooks
pp. 15-26
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Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
(Abstract)
Radu Teodorescu
Jun Nakano
Abhishek Tiwari
Josep Torrellas
pp. 27-42
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Session 2A: Instruction Scheduling
Optimal versus Heuristic Global Code Scheduling
(Abstract)
Sebastian Winkel
pp. 43-55
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Global Multi-Threaded Instruction Scheduling
(Abstract)
Guilherme Ottoni
David August
pp. 56-68
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Revisiting the Sequential Programming Model for Multi-Core
(Abstract)
Matthew Bridges
Neil Vachharajani
Yun Zhang
Thomas Jablin
David August
pp. 69-84
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Session 2B: Wear-Out Aware Architectures
Penelope: The NBTI-Aware Processor
(Abstract)
Jaume Abella
Xavier Vera
Antonio Gonz?lez
pp. 85-96
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Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
(Abstract)
Kypros Constantinides
Onur Mutlu
Todd Austin
Valeria Bertacco
pp. 97-108
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Self-calibrating Online Wearout Detection
(Abstract)
Jason Blome
Shuguang Feng
Shantanu Gupta
Scott Mahlke
pp. 109-122
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Session 3A: Memory
Implementing Signatures for Transactional Memory
(Abstract)
Daniel Sanchez
Luke Yen
Mark D. Hill
Karthikeyan Sankaralingam
pp. 123-133
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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
(Abstract)
Mrinmoy Ghosh
Hsien-Hsin S. Lee
pp. 134-145
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Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
(Abstract)
Onur Mutlu
Thomas Moscibroda
pp. 146-160
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Session 3B: Networking and Security
Impact of Cache Coherence Protocols on the Processing of Network Traffic
(Abstract)
Amit Kumar
Ram Huggahalli
pp. 161-171
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Flattened Butterfly Topology for On-Chip Networks
(Abstract)
John Kim
James Balfour
William Dally
pp. 172-182
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Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly
(Abstract)
Brian Rogers
Siddhartha Chhabra
Milos Prvulovic
Yan Solihin
pp. 183-196
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Session 4A: Reliability
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
(Abstract)
Jangwoo Kim
Nikos Hardavellas
Ken Mai
Babak Falsafi
James Hoe
pp. 197-209
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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
(Abstract)
Albert Meixner
Michael E. Bauer
Daniel Sorin
pp. 210-222
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Leveraging 3D Technology for Improved Reliability
(Abstract)
Niti Madan
Rajeev Balasubramonian
pp. 223-235
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Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
(Abstract)
Francisco Mesa-Mart?nez
Jose Renau
pp. 236-248
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Session 4B: Simulation/Workload Analysis
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
(Abstract)
Derek Chiou
Dam Sunwoo
Joonsoo Kim
Nikhil A. Patil
William Reinhart
Darrel Eric Johnson
Jebediah Keefe
Hari Angepat
pp. 249-261
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Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
(Abstract)
Christophe Dubach
Timothy Jones
Michael O?Boyle
pp. 262-271
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Informed Microarchitecture Design Space Exploration Using Workload Dynamics
(Abstract)
Chang-Burm Cho
Wangyuan Zhang
Tao Li
pp. 274-285
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Time Interpolation: So Many Metrics, So Few Registers
(Abstract)
Todd Mytkowicz
Peter F. Sweeney
Matthias Hauswirth
Amer Diwan
pp. 286-300
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Session 5: Prefetching and Snooping
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications
(Abstract)
Yuan Chou
pp. 301-313
ABSTRACT
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A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
(Abstract)
Jason Zebchuk
Elham Safi
Andreas Moshovos
pp. 314-327
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Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
(Abstract)
Karin Strauss
Xiaowei Shen
Josep Torrellas
pp. 327-342
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Session 6: Parallelism and QoS in CMPs
A Framework for Providing Quality of Service in Chip Multi-Processors
(Abstract)
Fei Guo
Yan Solihin
Li Zhao
Ravishankar Iyer
pp. 343-355
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A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
(Abstract)
William Thies
Vikram Chandrasekhar
Saman Amarasinghe
pp. 356-369
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Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
(Abstract)
Michael Chu
Rajiv Ravindran
Scott Mahlke
pp. 369-380
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Session 7: Parallel Architectures
Composable Lightweight Processors
(Abstract)
Changkyu Kim
Simha Sethumadhavan
M.S. Govindan
Nitya Ranganathan
Divya Gulati
Doug Burger
Stephen W. Keckler
pp. 381-394
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The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration
(Abstract)
Thomas Yeh
Petros Faloutsos
Milos Ercegovac
Sanjay Patel
Glenn Reinman
pp. 394-406
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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
(Abstract)
Wilson W.L. Fung
Ivan Sham
George Yuan
Tor M. Aamodt
pp. 407-420
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Session 8: Cache Replacement Policies
Scavenger: A New Last Level Cache Architecture with Global Block Priority
(Abstract)
Arkaprava Basu
Nevin Kirman
Meyrem Kirman
Mainak Chaudhuri
Jos? Mart?nez
pp. 421-432
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Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache
(Abstract)
Stephen Hines
David Whalley
Gary Tyson
pp. 433-444
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Emulating Optimal Replacement with a Shepherd Cache
(Abstract)
Kaushik Rajan
Govindarajan Ramaswamy
pp. 445-454
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Author Index
Author Index
(PDF)
pp. 455
ABSTRACT
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