CSDL - Proceedings M

38th Annual IEEE/ACM International Symposium on Microarchitecture - Copyright (PDF)

pp. iv

Introduction

Message from the General Chairs (PDF)

pp. viii-ix

Message from the Program Co-Chairs (PDF)

pp. x

Keynote I

The Cell Processor Architecture (PDF)

Jim Kahle, IBM

pp. 3

Session I: Register File and Memory System

How to Fake 1000 Registers (Abstract)

David W. Oehmke, University of Michigan, Ann Arbor

Nathan L. Binkert, University of Michigan, Ann Arbor

Trevor Mudge, University of Michigan, Ann Arbor

Steven K. Reinhardt, University of Michigan, Ann Arbor

pp. 7-18

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Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows (Abstract)

Stephen Hines, Florida State University

Gary Tyson, Florida State University

David Whalley, Florida State University

pp. 19-29

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Efficient Use of Invisible Registers in Thumb Code (Abstract)

Arvind Krishnaswamy, University of Arizona

Rajiv Gupta, University of Arizona

pp. 30-42

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Session II: Processor Design and Optimization

Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution (Abstract)

Hyesoon Kim, University of Texas at Austin

Onur Mutlu, University of Texas at Austin

Jared Stark, University of Texas at Austin

Yale N. Patt, Intel Corporation

pp. 43-54

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A Criticality Analysis of Clustering in Superscalar Processors (Abstract)

Pierre Salverda, University of Illinois at Urbana-Champaign

Craig Zilles, University of Illinois at Urbana-Champaign

pp. 55-66

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Incremental Commit Groups for Non-Atomic Trace Processing (Abstract)

Matt T. Yourst, State University of New York at Binghamton

Kanad Ghose, State University of New York at Binghamton

pp. 67-80

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Session III: Multithreading / CMP

Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities (Abstract)

Taku Ohsawa, NEC Corporation

Masamichi Takagi, NEC Corporation

Shoji Kawahara, NEC Corporation

Satoshi Matsushita, NEC Corporation

pp. 81-92

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Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor (Abstract)

Jiwei Lu, University of Minnesota, Twin Cities

Abhinav Das, University of Minnesota, Twin Cities

Wei-Chung Hsu, University of Minnesota, Twin Cities

Khoa Nguyen, Sun Microsystems Inc.

Santosh G. Abraham, Sun Microsystems Inc.

pp. 93-104

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Automatic Thread Extraction with Decoupled Software Pipelining (Abstract)

Guilherme Ottoni, Princeton University

Ram Rangan, Princeton University

Adam Stoler, Princeton University

David I. August, Princeton University

pp. 105-118

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Session IV: Compilers and Dynamic Optimization

Exploiting Vector Parallelism in Software Pipelined Loops (Abstract)

Samuel Larsen, MIT

Rodric Rabbah, MIT

Saman Amarasinghe, MIT

pp. 119-129

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Continuous Path and Edge Profiling (Abstract)

Michael D. Bond, University of Texas at Austin

Kathryn S. McKinley, University of Texas at Austin

pp. 130-140

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Improving Region Selection in Dynamic Optimization Systems (Abstract)

David Hiniker, Microsoft Corporation

Kim Hazelwood, University of Virginia

Michael D. Smith, Harvard University

pp. 141-154

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Keynote II

The Future Evolution of High-Performance Microprocessors (PDF)

Norm Jouppi, HP Labs

pp. 155

Session V: Memory Disambiguation and Optimization

Scalable Store-Load Forwarding via Store Queue Index Prediction (Abstract)

Tingting Sha, University of Pennsylvania

Milo M.K. Martin, University of Pennsylvania

Amir Roth, University of Pennsylvania

pp. 159-170

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Address-Indexed Memory Disambiguation and Store-to-Load Forwarding (Abstract)

Sam S. Stone, University of Illinois, Urbana-Champaign

Kevin M. Woley, University of Illinois, Urbana-Champaign

Matthew I. Frank, University of Illinois, Urbana-Champaign

pp. 171-182

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Store Memory-Level Parallelism Optimizations for Commercial Applications (Abstract)

Yuan Chou, Sun Microsystems

Lawrence Spracklen, Sun Microsystems

Santosh G. Abraham, Sun Microsystems

pp. 183-196

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Session VI: Processor Design

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors (Abstract)

Fred A. Bower, Computer Science, Duke University

Daniel J. Sorin, Computer Engineering, Duke University

Sule Ozev, Computer Engineering, Duke University

pp. 197-208

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uComplexity: Estimating Processor Design Effort (Abstract)

Cyrus Bazeghi, University of California Santa Cruz

Francisco J. Mesa-Martinez, University of California Santa Cruz

Jose Renau, University of California Santa Cruz

pp. 209-218

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Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System (Abstract)

Kevin Fan, University of Michigan, Ann Arbor

Manjunath Kudlur, University of Michigan, Ann Arbor

Hyunchul Park, University of Michigan, Ann Arbor

Scott Mahlke, University of Michigan, Ann Arbor

pp. 219-232

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Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns (Abstract)

Session VII: Speculation

Onur Mutlu, University of Texas at Austin

Hyesoon Kim, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

pp. 233-244

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Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors (Abstract)

Meyrem K?, Cornell University

Nevin K?, Cornell University

Jose F. Mart?, Cornell University

pp. 245-256

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ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing (Abstract)

Smruti R. Sarangi, University of Illinois at Urbana-Champaign

Wei Liu, Josep Torrellas, University of Illinois at Urbana-Champaign

Yuanyuan Zhou, University of Illinois at Urbana-Champaign

pp. 257-270

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Session VIII: Power, Temperature and Fault Management

A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance (Abstract)

Qiang Wu, Princeton University

Margaret Martonosi, Princeton University

Douglas W. Clark, Princeton University

V.J. Reddi, Univ. of Colorado at Boulder

Dan Connors, Univ. of Colorado at Boulder

Youfeng Wu, 3Programming Systems Lab, Corporate Tech. Group, Intel Corporation

Jin Lee, 3Programming Systems Lab, Corporate Tech. Group, Intel Corporation

David Brooks, Harvard University

pp. 271-282

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Thermal Management of On-Chip Caches Through Power Density Minimization (Abstract)

Ja Chun Ku, Northwestern University

Serkan Ozdemir, Northwestern University

Gokhan Memik, Northwestern University

Yehea Ismail, Northwestern University

pp. 283-293

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Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines (Abstract)

Michael D. Powell, Purdue University

Ethan Schuchman, Purdue University

T. N. Vijaykumar, Purdue University

pp. 294-304

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A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation (Abstract)

Tzvetan S. Metodi, University Of California at Davis

Darshan D. Thaker, University Of California at Davis

Andrew W. Cross, Massachusetts Institute of Technology

pp. 305-318

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Session IX: Processor Architecture and Programming

"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense (Abstract)

Ronald D. Barnes, George Mason University

Shane Ryoo, University of Illinois at Urbana-Champaign

Wen-mei W. Hwu, University of Illinois at Urbana-Champaign

pp. 319-330

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The TM3270 Media-Processor (Abstract)

Jan-Willem van de Waerdt, Philips Semiconductors

Stamatis Vassiliadis, Delft, the Netherlands

Sanjeev Das, Philips Semiconductors

Sebastian Mirolo, Philips Semiconductors

Chris Yen, Philips Semiconductors

Bill Zhong, Philips Semiconductors

Carlos Basto, Philips Semiconductors

Jean-Paul van Itegem, Philips Semiconductors

Dinesh Amirtharaj, Philips Semiconductors

Kulbhushan Kalra, Philips Semiconductors

Pedro Rodriguez, Philips Semiconductors

Hans van Antwerpen, Philips Semiconductors

pp. 331-342

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Stream Programming on General-Purpose Processors (Abstract)

Jayanth Gummaraju, Stanford University

Mendel Rosenblum, Stanford University

pp. 343-354

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Shader Performance Analysis on a Modern GPU Architecture (Abstract)

Victor Moya, Universitat Polit?cnica de Catalunya

Carlos Gonzalez, Universitat Polit?cnica de Catalunya

Jordi Roca, Universitat Polit?cnica de Catalunya

Agustin Fernandez, Universitat Polit?cnica de Catalunya

Roger Espasa, Universitat Polit?cnica de Catalunya

pp. 355-364

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Author Index

Author Index (PDF)

pp. 365