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  • 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'04)
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37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'04)
Portland,Oregon
December 04-December 08
ISBN: 0-7695-2126-6
Table of Contents
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Reviewers (PDF)
pp. xii-xiii
Keynote 1
Session 1: Instruction Collapsing
Anne Bracy, University of Pennsylvania
Prashant Prahlad, University of Pennsylvania
Amir Roth, University of Pennsylvania
pp. 18-29
Nathan Clark, University of Michigan - Ann Arbor
Manjunath Kudlur, University of Michigan - Ann Arbor
Hyunchul Park, University of Michigan - Ann Arbor
Scott Mahlke, University of Michigan - Ann Arbor
Kriszti? Flautner, ARM Ltd., UK
pp. 30-40
Session 2: Performance Evaluation
Daniel Gracia P?rez, LRI, Paris Sud/11 University, France
Gilles Mouchard, LRI, Paris Sud/11 University, France
Olivier Temam, LRI, Paris Sud/11 University, France
pp. 43-54
Li Shang, Princeton University, NJ
Li-Shiuan Peh, Princeton University, NJ
Amit Kumar, Princeton University, NJ
Niraj K. Jha, Princeton University, NJ
pp. 67-78
Session 3: Trace Analysis
Murali Annavaram, Microarchitecture Research Lab (MRL)
Ryan Rakvic, Microarchitecture Research Lab (MRL)
Marzia Polito, Systems Technology Labs (STL)
Jean-Yves Bouguet, Systems Technology Labs (STL)
Richard Hankins, Microarchitecture Research Lab (MRL)
Bob Davies, Systems Technology Labs (STL)
pp. 93-104
Xiangyu Zhang, The University of Arizona, Tucson
Rajiv Gupta, The University of Arizona, Tucson
pp. 105-116
Session 4: Control Flow
David N. Armstrong, The University of Texas at Austin
Hyesoon Kim, The University of Texas at Austin
Onur Mutlu, The University of Texas at Austin
Yale N. Patt, The University of Texas at Austin
pp. 119-128
Jamison D. Collins, University of California, San Diego
Dean M. Tullsen, University of California, San Diego
Hong Wang, Intel Corporation, Santa Clara, CA
pp. 129-140
Keynote 2
Session 5: Adaptive Microarchitectures
Arindam Mallik, Northwestern University
Gokhan Memik, Northwestern University
pp. 147-156
Steven Dropsho, University of Rochester
Greg Semeraro, University of Rochester
David H. Albonesi, University of Rochester
Grigorios Magklis, University of Rochester
Michael L. Scott, University of Rochester
pp. 157-168
Session 6: Multithreaded/Multicore Processors
Francisco J. Cazorla, Universitat Polit?cnica de Catalunya, Spain
Alex Ramirez, Universitat Polit?cnica de Catalunya, Spain
Mateo Valero, Universitat Polit?cnica de Catalunya, Spain
Enrique Fern?ndez, Universidad de Las Palmas de Gran Canaria, Spain
pp. 171-182
Eric Tune, University of California at San Diego
Rakesh Kumar, University of California at San Diego
Dean M. Tullsen, University of California at San Diego
Brad Calder, University of California at San Diego
pp. 183-194
Rakesh Kumar, University of California, San Diego
Norman P. Jouppi, HP Labs, Palo Alto, CA
Dean M. Tullsen, University of California, San Diego
pp. 195-206
Session 7: Security
Nathan Tuck, University of California, San Diego
Brad Calder, University of California, San Diego
George Varghese, University of California, San Diego
pp. 209-220
Neil Vachharajani, Princeton University
Matthew J. Bridges, Princeton University
Jonathan Chang, Princeton University
Ram Rangan, Princeton University
Guilherme Ottoni, Princeton University
Jason A. Blome, Princeton University
George A. Reis, Princeton University
Manish Vachharajani, Princeton University
David I. August, Princeton University
pp. 243-254
Session 8: Reliability
Jared C. Smolens, Carnegie Mellon University, Pittsburgh, PA
Jangwoo Kim, Carnegie Mellon University, Pittsburgh, PA
James C. Hoe, Carnegie Mellon University, Pittsburgh, PA
Babak Falsafi, Carnegie Mellon University, Pittsburgh, PA
pp. 257-268
Pin Zhou, University of Illinois at Urbana-Champaign
Wei Liu, University of Illinois at Urbana-Champaign
Long Fei, Purdue University
Shan Lu, University of Illinois at Urbana-Champaign
Feng Qin, University of Illinois at Urbana-Champaign
Yuanyuan Zhou, University of Illinois at Urbana-Champaign
Samuel Midkiff, Purdue University
Josep Torrellas, University of Illinois at Urbana-Champaign
pp. 269-280
Session 9: Code Generation and Optimization
Ghassan Shobaki, University of California, Davis
Kent Wilken, University of California, Davis
pp. 283-293
Gerolf Hoflehner, Intel? Compiler Lab, Santa Clara, California
Knud Kirkegaard, Intel? Compiler Lab, Santa Clara, California
Rod Skinner, Intel? Compiler Lab, Santa Clara, California
Daniel Lavery, Intel? Compiler Lab, Santa Clara, California
Yong-fong Lee, Intel? Compiler Lab, Santa Clara, California
Wei Li, Intel? Compiler Lab, Santa Clara, California
pp. 294-303
Oguz Ergin, Intel Labs, UPC, Barcelona, Spain
Deniz Balkan, State University of New York, Binghamton, NY
Kanad Ghose, State University of New York, Binghamton, NY
Dmitry Ponomarev, State University of New York, Binghamton, NY
pp. 304-315
Session 10: Caches and Memory
Bradford M. Beckmann, University of Wisconsin-Madison
David A. Wood, University of Wisconsin-Madison
pp. 319-330
Christopher Batten, MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Ronny Krashinsky, MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Steve Gerding, MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanovic, MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
pp. 331-342
Ibrahim Hur, The University of Texas at Austin; IBM Corporation, Austin, TX
Calvin Lin, The University of Texas at Austin
pp. 343-354
Author Index (PDF)
pp. 367-367
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