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36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'03)
San Diego, California
December 03-December 05
ISBN: 0-7695-2043-X
Table of Contents
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Keynote 1
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Kerry Bernstein, IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 3
Session 1: Voltage Scaling and Transient Faults
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Dan Ernst, The University of Michigan, Ann Arbor
Nam Sung Kim, The University of Michigan, Ann Arbor
Shidhartha Das, The University of Michigan, Ann Arbor
Sanjay Pant, The University of Michigan, Ann Arbor
Rajeev Rao, The University of Michigan, Ann Arbor
Toan Pham, The University of Michigan, Ann Arbor
Conrad Ziesler, The University of Michigan, Ann Arbor
David Blaauw, The University of Michigan, Ann Arbor
Todd Austin, The University of Michigan, Ann Arbor
Krisztian Flautner, ARM Ltd, Cambridge, UK
Trevor Mudge, The University of Michigan, Ann Arbor
pp. 7
Shubhendu S. Mukherjee, Intel Corporation
Christopher Weaver, Intel Corporation; University of Michigan
Joel Emer, Intel Corporation
Steven K. Reinhardt, Intel Corporation; University of Michigan
Todd Austin, University of Michigan
pp. 29
Session 2: Cache Design
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Bradford M. Beckmann, University of Wisconsin, Madison
David A. Wood, University of Wisconsin, Madison
pp. 43
Session 3: Power and Energy Efficient Architectures
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A. Hartstein, IBM - T. J. Watson Research Center, Yorktown Heights, NY
Thomas R. Puzak, IBM - T. J. Watson Research Center, Yorktown Heights, NY
pp. 117
Session 4: Application Specific Optimization and Analysis
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Nathan Clark, University of Michigan, Ann Arbor
Hongtao Zhong, University of Michigan, Ann Arbor
Scott Mahlke, University of Michigan, Ann Arbor
pp. 129
Silviu Ciricescu, Motorola Labs, Motorola, Schaumburg, IL
Ray Essick, Motorola Labs, Motorola, Schaumburg, IL
Brian Lucas, Motorola Labs, Motorola, Schaumburg, IL
Phil May, Motorola Labs, Motorola, Schaumburg, IL
Kent Moat, Motorola Labs, Motorola, Schaumburg, IL
Jim Norris, Motorola Labs, Motorola, Schaumburg, IL
Michael Schuette, Motorola Labs, Motorola, Schaumburg, IL
Ali Saidi, The Mitre Corporation, Bedford, MA
pp. 141
Richard Hankins, Intel? Corporation
Trung Diep, Intel? Corporation
Murali Annavaram, Intel? Corporation
Brian Hirano, Oracle? Corporation
Harald Eri, Oracle? Corporation
Hubert Nueckel, Intel? Corporation
John P. Shen, Intel? Corporation
pp. 151
Keynote 2
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Michael Schlansker, Hewlett-Packard Laboratories
pp. 165
Session 5: Dynamic Optimization Systems
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Jiwei Lu, University of Minnesota, Twin Cities
Howard Chen, University of Minnesota, Twin Cities
Rao Fu, University of Minnesota, Twin Cities
Wei-Chung Hsu, University of Minnesota, Twin Cities
Bobbie Othmer, University of Minnesota, Twin Cities
Pen-Chung Yew, University of Minnesota, Twin Cities
Dong-Yuan Chen, Intel Corporation
pp. 180
Session 6: Dynamic Program Analysis and Optimization
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Vikram Adve, University of Illinois at Urbana-Champaign
Chris Lattner, University of Illinois at Urbana-Champaign
Michael Brukman, University of Illinois at Urbana-Champaign
Anand Shukla, University of Illinois at Urbana-Champaign
Brian Gaeke, University of Illinois at Urbana-Champaign
pp. 205
Ashutosh S. Dhodapkar, University of Wisconsin - Madison
James E. Smith, University of Wisconsin - Madison
pp. 217
Brian A. Fields, University of California-Berkeley
Rastislav Bod?, University of California-Berkeley
Mark D. Hill, University of Wisconsin-Madison
Chris J. Newburn, Intel Corporation
pp. 228
Session 7: Branch, Value and Scheduling Optimizations
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Ho-Seop Kim, University of Wisconsin - Madison
James E. Smith, University of Wisconsin - Madison
pp. 253
Ilhyun Kim, University of Wisconsin, Madison
Mikko H. Lipasti, University of Wisconsin, Madison
pp. 277
Session 8: Dataflow, Data Parallel, and Clustered Architectures
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WaveScalar (Abstract)
Steven Swanson, University of Washington
Ken Michelson, University of Washington
Andrew Schwerin, University of Washington
Mark Oskin, University of Washington
pp. 291
Karthikeyan Sankaralingam, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
William R. Mark, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
pp. 303
Enric Gibert, Universitat Polit?cnica de Catalunya
Jes? S?nchez, Intel Labs - Universitat Polit?cnica de Catalunya
Antonio Gonz?lez, Universitat Polit?cnica de Catalunya; Intel Labs - Universitat Polit?cnica de Catalunya
pp. 315
Alex Alet?, UPC, Barcelona, Spain
Josep M. Codina, UPC, Barcelona, Spain
Antonio Gonz?lez, UPC, Barcelona, Spain; Intel Barcelona Research Center, Intel Labs, UPC, Barcelona, Spain
David Kaeli, Northeastern University, Boston, MA, USA
pp. 326
Session 9: Secure and Network Processors
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G. Edward Suh, MIT Computer Science and Artificial Intelligence Laboratory
Dwaine Clarke, MIT Computer Science and Artificial Intelligence Laboratory
Blaise Gassend, MIT Computer Science and Artificial Intelligence Laboratory
Marten van Dijk, MIT Computer Science and Artificial Intelligence Laboratory
Srinivas Devadas, MIT Computer Science and Artificial Intelligence Laboratory
pp. 339
Jun Yang, University of California, Riverside
Youtao Zhang, University of Texas at Dallas
Lan Gao, University of California, Riverside
pp. 351
Jorge Garc?, Polytechnic University of Catalonia
Jes? Corbal, Polytechnic University of Catalonia
Lloren? Cerd?, Polytechnic University of Catalonia
Mateo Valero, Polytechnic University of Catalonia
pp. 373
Session 10: Scaling Design
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Ronald D. Barnes, University of Illinois at Urbana-Champaign
Erik M. Nystrom, University of Illinois at Urbana-Champaign
John W. Sias, University of Illinois at Urbana-Champaign
Sanjay J. Patel, University of Illinois at Urbana-Champaign
Nacho Navarro, University of Illinois at Urbana-Champaign
Wen-mei W. Hwu, University of Illinois at Urbana-Champaign
pp. 387
Simha Sethumadhavan, The University of Texas at Austin
Rajagopalan Desikan, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
Charles R. Moore, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
pp. 399
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