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35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'02)
Istanbul, Turkey
November 18-November 22
ISBN: 0-7695-1959-1
Table of Contents
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Session 1: Superscalar Design
José F. Martínez, Cornell University
Jose Renau, University of Illinois at Urbana-Champaign
Michael C. Huang, University of Rochester
Milos Prvulovic, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
pp. 3
J. Adam Butts, University of Wisconsin-Madison
Gurindar S. Sohi, University of Wisconsin-Madison
pp. 15
Vlad Petric, University of Pennsylvania
Anne Bracy, University of Pennsylvania
Amir Roth, University of Pennsylvania
pp. 37
Session 2: Multithreading I
Gregory A. Muthler, University of Illinois at Urbana-Champaign
David Crowe, University of Illinois at Urbana-Champaign
Sanjay J. Patel, University of Illinois at Urbana-Champaign
Steven S. Lumetta, University of Illinois at Urbana-Champaign
pp. 51
Jamison Collins, University of California, San Diego
Suleyman Sair, University of California, San Diego
Brad Calder, University of California, San Diego
Dean M. Tullsen, University of California, San Diego
pp. 62
Robert S. Chappell, The University of Michigan
Francis Tseng, The University of Texas at Austin
Adi Yoaz, Intel Corporation
Yale N. Patt, The University of Texas at Austin
pp. 74
Craig Zilles, University of Illinois at Urbana-Champaign
Gurindar Sohi, University of Wisconsin at Madison
pp. 85
Session 3: Compiler Scheduling
Walter Lee, Massachusetts Institute of Technology
Diego Puppin, Massachusetts Institute of Technology
Shane Swenson, Massachusetts Institute of Technology
Saman Amarasinghe, Massachusetts Institute of Technology
pp. 111
Enric Gibert, Universitat Polit?cnica de Catalunya
Jesús Sánchez, Intel Labs - Universitat Polit?cnica de Catalunya
Antonio González, Intel Labs - Universitat Polit?cnica de Catalunya
pp. 123
Youfeng Wu, Intel Corporation
Ryan Rakvic, Intel Corporation
Li-Ling Chen, Intel Corporation
Chyi-Chang Miao, Intel Corporation
George Chrysos, Intel Corporation
Jesse Fang, Intel Corporation
pp. 134
Session 4: Register File and Memory System Design
Jesus Corbal, Universitat Polit?cnica de Catalunya
Roger Espasa, Universitat Polit?cnica de Catalunya
Mateo Valero, Universitat Polit?cnica de Catalunya
pp. 149
Steven Hsu, Intel Corporation
Shih-Lien Lu, Intel Corporation
Shih-Chang Lai, Oregon State University
Ram Krishnamurthy, Intel Corporation
Konrad Lai, Intel Corporation
pp. 161
Session 5: Energy Efficient Memory Systems
I. Kadayif, Pennsylvania State University
A. Sivasubramaniam, Pennsylvania State University
M. Kandemir, Pennsylvania State University
G. Kandiraju, Pennsylvania State University
G. Chen, Pennsylvania State University
pp. 185
Jun Yang, University of California, Riverside
Rajiv Gupta, University of Arizona
pp. 197
W. Zhang, Pennsylvania State University
J.S. Hu, Pennsylvania State University
V. Degalahal, Pennsylvania State University
M. Kandemir, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
M.J. Irwin, Pennsylvania State University
pp. 208
Session 6: Compilation and Run-time Systems
Ronald D. Barnes, University of Illinois at Urbana-Champaign
Erik M. Nystrom, University of Illinois at Urbana-Champaign
Matthew C. Merten, University of Illinois at Urbana-Champaign
Wen-mei W. Hwu, University of Illinois at Urbana-Champaign
pp. 233
Changqing Fu, University of California, Davis
Kent Wilken, University of California, Davis
pp. 245
Giuseppe Desoli, Hewlett-Packard Laboratories
Nikolay Mateev, Hewlett-Packard Laboratories
Evelyn Duesterwald, Hewlett-Packard Laboratories
Paolo Faraboschi, Hewlett-Packard Laboratories
Joseph A. Fisher, Hewlett-Packard Laboratories
pp. 257
Session 7: Simulation and Architecture Evaluation
Manish Vachharajani, Princeton University
Neil Vachharajani, Princeton University
David A. Penry, Princeton University
Jason A. Blome, Princeton University
David I. August, Princeton University
pp. 271
Hang-Sheng Wang, Princeton University
Xinping Zhu, Princeton University
Li-Shiuan Peh, Princeton University
Sharad Malik, Princeton University
pp. 294
Session 8: Energy Aware Design
Steven Dropsho, University of Rochester
Volkan Kursun, University of Rochester
David H. Albonesi, University of Rochester
Sandhya Dwarkadas, University of Rochester
Eby G. Friedman, University of Rochester
pp. 321
Viji Srinivasan, IBM T.J. Watson Research Center
David Brooks, IBM T.J. Watson Research Center
Michael Gschwind, IBM T.J. Watson Research Center
Pradip Bose, IBM T.J. Watson Research Center
Victor Zyuban, IBM T.J. Watson Research Center
Philip N. Strenski, IBM T.J. Watson Research Center
Philip G. Emma, IBM T.J. Watson Research Center
pp. 333
K. Basu, Northwestern University
A. Choudhary, Northwestern University
J. Pisharath, Northwestern University
M. Kandemir, Pennsylvania State University
pp. 345
Greg Semeraro, University of Rochester
David H. Albonesi, University of Rochester
Steven G. Dropsho, University of Rochester
Grigorios Magklis, University of Rochester
Sandhya Dwarkadas, University of Rochester
Michael L. Scott, University of Rochester
pp. 356
Session 9: Superscalar Microarchitecture
Alex Ramirez, Universitat Politecnica de Catalunya
Oliverio J. Santana, Universitat Politecnica de Catalunya
Josep L. Larriba-Pey, Universitat Politecnica de Catalunya
Mateo Valero, Universitat Politecnica de Catalunya
pp. 371
Session 10: Multithreading II
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