CSDL - Proceedings M

Organizing Committee (PDF)

pp. x

Program Committee (PDF)

pp. xi

Reviewers (PDF)

pp. xii

Session 1: Superscalar Design

Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors (Abstract)

José F. Martínez, Cornell University

Jose Renau, University of Illinois at Urbana-Champaign

Michael C. Huang, University of Rochester

Milos Prvulovic, University of Illinois at Urbana-Champaign

Josep Torrellas, University of Illinois at Urbana-Champaign

pp. 3

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Characterizing and Predicting Value Degree of Use (Abstract)

J. Adam Butts, University of Wisconsin-Madison

Gurindar S. Sohi, University of Wisconsin-Madison

pp. 15

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Hierarchical Scheduling Windows (Abstract)

Edward Brekelbaum, Intel Labs

Jeff Rupley II, Intel Labs

Chris Wilkerson, Intel Labs

Bryan Black, Intel Labs

pp. 27

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Three Extensions To Register Integration (Abstract)

Vlad Petric, University of Pennsylvania

Anne Bracy, University of Pennsylvania

Amir Roth, University of Pennsylvania

pp. 37

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Session 2: Multithreading I

Instruction Fetch Deferral using Static Slack (Abstract)

Gregory A. Muthler, University of Illinois at Urbana-Champaign

David Crowe, University of Illinois at Urbana-Champaign

Sanjay J. Patel, University of Illinois at Urbana-Champaign

Steven S. Lumetta, University of Illinois at Urbana-Champaign

pp. 51

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Pointer Cache Assisted Prefetching (Abstract)

Jamison Collins, University of California, San Diego

Suleyman Sair, University of California, San Diego

Brad Calder, University of California, San Diego

Dean M. Tullsen, University of California, San Diego

pp. 62

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Microarchitectural Support for Precomputation Microthreads (Abstract)

Robert S. Chappell, The University of Michigan

Francis Tseng, The University of Texas at Austin

Adi Yoaz, Intel Corporation

Yale N. Patt, The University of Texas at Austin

pp. 74

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Master/Slave Speculative Parallelization (Abstract)

Craig Zilles, University of Illinois at Urbana-Champaign

Gurindar Sohi, University of Wisconsin at Madison

pp. 85

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Session 3: Compiler Scheduling

Reduced Code Size Modulo Scheduling in the Absence of Hardware Support (Abstract)

Josep Llosa, Universitat Polit?cnica de Catalunya

Stefan M. Freudenberger, Hewlett-Packard Laboratories

pp. 99

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Convergent Scheduling (Abstract)

Walter Lee, Massachusetts Institute of Technology

Diego Puppin, Massachusetts Institute of Technology

Shane Swenson, Massachusetts Institute of Technology

Saman Amarasinghe, Massachusetts Institute of Technology

pp. 111

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Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor (Abstract)

Enric Gibert, Universitat Polit?cnica de Catalunya

Jesús Sánchez, Intel Labs - Universitat Polit?cnica de Catalunya

Antonio González, Intel Labs - Universitat Polit?cnica de Catalunya

pp. 123

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Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors (Abstract)

Youfeng Wu, Intel Corporation

Ryan Rakvic, Intel Corporation

Li-Ling Chen, Intel Corporation

Chyi-Chang Miao, Intel Corporation

George Chrysos, Intel Corporation

Jesse Fang, Intel Corporation

pp. 134

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Session 4: Register File and Memory System Design

Three-Dimensional Memory Vectorization for High Bandwidth Media Memory Systems (Abstract)

Jesus Corbal, Universitat Polit?cnica de Catalunya

Roger Espasa, Universitat Polit?cnica de Catalunya

Mateo Valero, Universitat Polit?cnica de Catalunya

pp. 149

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Dynamic Addressing Memory Arrays with Physical Locality (Abstract)

Steven Hsu, Intel Corporation

Shih-Lien Lu, Intel Corporation

Shih-Chang Lai, Oregon State University

Ram Krishnamurthy, Intel Corporation

Konrad Lai, Intel Corporation

pp. 161

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Reducing Register Ports for Higher Speed and Lower Energy (Abstract)

Il Park, Purdue University

Michael D. Powell, Purdue University

T.N. Vijaykumar, Purdue University

pp. 171

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Session 5: Energy Efficient Memory Systems

Generating Physical Addresses Directly for Saving Instruction TLB Energy (Abstract)

I. Kadayif, Pennsylvania State University

A. Sivasubramaniam, Pennsylvania State University

M. Kandemir, Pennsylvania State University

G. Kandiraju, Pennsylvania State University

G. Chen, Pennsylvania State University

pp. 185

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Energy Efficient Frequent Value Data Cache Design (Abstract)

Jun Yang, University of California, Riverside

Rajiv Gupta, University of Arizona

pp. 197

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Compiler-Directed Instruction Cache Leakage Optimization (Abstract)

W. Zhang, Pennsylvania State University

J.S. Hu, Pennsylvania State University

V. Degalahal, Pennsylvania State University

M. Kandemir, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

M.J. Irwin, Pennsylvania State University

pp. 208

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Leakage Power Reduction using Dynamic Voltage Scaling and Cahe Sub-bank Prediction (Abstract)

Nam Sung Kim, University of Michigan

Krisztián Flautner, ARM Ltd

David Blaauw, University of Michigan

Trevor Mudge, University of Michigan

pp. 219

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Session 6: Compilation and Run-time Systems

Vacuum Packing: Extracting Hardware-Detected Program Phases for Post-Link Optimization (Abstract)

Ronald D. Barnes, University of Illinois at Urbana-Champaign

Erik M. Nystrom, University of Illinois at Urbana-Champaign

Matthew C. Merten, University of Illinois at Urbana-Champaign

Wen-mei W. Hwu, University of Illinois at Urbana-Champaign

pp. 233

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A Faster Optimal Register Allocator (Abstract)

Changqing Fu, University of California, Davis

Kent Wilken, University of California, Davis

pp. 245

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DELI: A New Run-Time Control Point (Abstract)

Giuseppe Desoli, Hewlett-Packard Laboratories

Nikolay Mateev, Hewlett-Packard Laboratories

Evelyn Duesterwald, Hewlett-Packard Laboratories

Paolo Faraboschi, Hewlett-Packard Laboratories

Joseph A. Fisher, Hewlett-Packard Laboratories

pp. 257

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Session 7: Simulation and Architecture Evaluation

Microarchitectural Exploration with Liberty (Abstract)

Manish Vachharajani, Princeton University

Neil Vachharajani, Princeton University

David A. Penry, Princeton University

Jason A. Blome, Princeton University

David I. August, Princeton University

pp. 271

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Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks (Abstract)

Christoforos Kozyrakis, Stanford University

David Patterson, University of California at Berkeley

pp. 283

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Orion: A Power-Performance Simulator for Interconnection Networks (Abstract)

Hang-Sheng Wang, Princeton University

Xinping Zhu, Princeton University

Li-Shiuan Peh, Princeton University

Sharad Malik, Princeton University

pp. 294

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Using Modern Graphics Architectures for General-Purpose Computing: A Framework and Analysis (Abstract)

Chris J. Thompson, University of Washington

Sahngyun Hahn, University of Washington

Mark Oskin, University of Washington

pp. 306

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Session 8: Energy Aware Design

Managing Static Leakage Energy in Microprocessor Functional Units (Abstract)

Steven Dropsho, University of Rochester

Volkan Kursun, University of Rochester

David H. Albonesi, University of Rochester

Sandhya Dwarkadas, University of Rochester

Eby G. Friedman, University of Rochester

pp. 321

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Optimizing Pipelines for Power and Performance (Abstract)

Viji Srinivasan, IBM T.J. Watson Research Center

David Brooks, IBM T.J. Watson Research Center

Michael Gschwind, IBM T.J. Watson Research Center

Pradip Bose, IBM T.J. Watson Research Center

Victor Zyuban, IBM T.J. Watson Research Center

Philip N. Strenski, IBM T.J. Watson Research Center

Philip G. Emma, IBM T.J. Watson Research Center

pp. 333

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Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses (Abstract)

K. Basu, Northwestern University

A. Choudhary, Northwestern University

J. Pisharath, Northwestern University

M. Kandemir, Pennsylvania State University

pp. 345

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Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture (Abstract)

Greg Semeraro, University of Rochester

David H. Albonesi, University of Rochester

Steven G. Dropsho, University of Rochester

Grigorios Magklis, University of Rochester

Sandhya Dwarkadas, University of Rochester

Michael L. Scott, University of Rochester

pp. 356

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Session 9: Superscalar Microarchitecture

Fetching instruction streams (Abstract)

Alex Ramirez, Universitat Politecnica de Catalunya

Oliverio J. Santana, Universitat Politecnica de Catalunya

Josep L. Larriba-Pey, Universitat Politecnica de Catalunya

Mateo Valero, Universitat Politecnica de Catalunya

pp. 371

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Register Write Specialization Register Read Specialization: A Path to Complexity-Effective Wide-Issue Superscalar Processors (Abstract)

André Seznec, IRISA/INRIA

Eric Toullec, IRISA/INRIA

Olivier Rochecouste, IRISA/INRIA

pp. 383

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Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth (Abstract)

Gabriel H. Loh, Yale University

pp. 395

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Session 10: Multithreading II

Microarchitectural Denial of Service: Insuring Microarchitectural Fairness (Abstract)

Dirk Grunwald, University of Colorado

Soraya Ghiasi, University of Colorado

pp. 409

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Compiling for Instruction Cache Performance on a Multithreaded Architecture (Abstract)

Rakesh Kumar, University of California, San Diego

Dean M. Tullsen, University of California, San Diego

pp. 419

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A Quantitative Framework for Automated Pre-Execution Thread Selection (Abstract)

Amir Roth, University of Pennsylvania

Gurindar S. Sohi, University of Wisconsin-Madison

pp. 430

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Author Index (PDF)

pp. 443