Message from the General Chair

Message from the Program Chair (PDF)

pp. x

Committees (PDF)

pp. xi

Reviewers (PDF)

pp. xiii

Keynote

Fifty Years of Microarchitecture (Abstract)

Harvey Cragon

pp. 2

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Session 1: Novel Ideas

Skipper: A Microarchitecture for Exploiting Control-Flow Independence (Abstract)

Chen-Yong Cher

T.N. Vijaykumar

pp. 4

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Performance Characterization of a Hardware Mechanism for Dynamic Optimization (Abstract)

pp. 16

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Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems (Abstract)

Eric Rotenberg

pp. 28

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Karthikeyan Sankaralingam

A Design Space Evaluation of Grid Processor Architectures (Abstract)

Ramadass Nagarajan

Doug Burger

Stephen W. Keckler

pp. 40

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Session 2: Memory Hierarchies

Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping (Abstract)

pp. 54

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A Code Decompression Architecture for VLIW Processors (Abstract)

pp. 66

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Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate (Abstract)

pp. 76

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Session 3: Energy Efficient Architectures

Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources (Abstract)

pp. 90

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Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction (Abstract)

Y. Tsai

pp. 102

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Reducing Power with Dynamic Critical Path Information (Abstract)

pp. 0114

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Direct Addressed Caches for Reduced Power Consumption (Abstract)

pp. 124

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Emerging Applications for the Connected Home (Abstract)

Adrew Wolfe

pp. 136

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Session 4: Modulo Scheduling

Modulo Schedule Buffers (Abstract)

Matthew Merten

Wen-mei Hwu

pp. 138

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Graph-Partitioning Based Instruction Scheduling for Clustered Processors (Abstract)

pp. 150

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Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures (Abstract)

pp. 160

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Session 5: Compilation

Efficient Static Single Assignment Form for Predication (Abstract)

Arthur Stoutchinin

Francois de Ferriere

pp. 172

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The Impact of If-Conversion and Branch Prediction on Program Execution on the Intel Itanium Processor (Abstract)

pp. 182

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Mapping Reference Code to Irregular DSPs within the Retargetable, Optimizing Compiler COGEN(T) (Abstract)

Gary Gréwal

Charles Thomas Wilson

pp. 192

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Session 6: Superscalar Architectures

Select-Free Instruction Scheduling Logic (Abstract)

pp. 204

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Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery (Abstract)

pp. 214

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A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors (Abstract)

pp. 225

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Reducing the Complexity of the Register File in Dynamic Superscalar Processors (Abstract)

Rajeev Balasubramonian

Sandhya Dwarkadas

David H. Albonesi

pp. 037

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Session 7: Multimedia and Graphics

Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications (Abstract)

Christopher J. Hughes

Jayanh Srinivasan

Sarita V. Adve

pp. 250

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Enhancing Loop Buffering of Media and Telecommunications Applications using Low-Overhead Predication (Abstract)

pp. 262

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Cool-Cache for Hot Multimedia (Abstract)

pp. 274

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ZR: A 3D API Transparent Technology for Chunk Rendering (Abstract)

pp. 284

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Session 8: Multithreading and Value Prediction

Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution (Abstract)

Ravi Rajwar

James Goodman

pp. 294

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Dynamic Speculative Precomputation (Abstract)

pp. 306

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Handling Long-latency Loads in a Simultaneous Multithreading Processor (Abstract)

Dean M. Tullsen

Jeffery A. Brown

pp. 318

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Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing (Abstract)

pp. 328

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Index of Authors (PDF)

pp. 0339