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  • 33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'00)
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33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'00)
Monterey, California
December 10-December 13
ISBN: 0-7695-0924-x
Table of Contents
Introduction
Keynote Speakers
Memory Hierarchy I
Kevin M. Lepak, University of Wisconsin
Mikko H. Lipasti, University of Wisconsin
pp. 22
Timothy Sherwood, University of California, San Diego
Suleyman Sair, University of California, San Diego
Brad Calder, University of California, San Diego
pp. 42
Superscalar Architecture I
Jared Stark, Intel Corporation
Mary D. Brown, The University of Texas at Austin
Yale N. Patt, The University of Texas at Austin
pp. 57
Daniel A. JimCnez, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Calvin Lin, The University of Texas at Austin
pp. 67
Stevan Vlaovic, The University of Michigan
Edward S. Davidson, The University of Michigan
Gary S. Tyso, The University of Michigan
pp. 77
Chris Weaver, University of Michigan
Todd Austin, University of Michigan
Saugata Chatterjee, University of Michigan
pp. 87
Compilation
Alexandre Eichenberger, North Carolina State University, Raleigh, NC
Waleed Meleis, Northeastern University, Boston, MA
Suman Maradani, Northeastern University, Boston, MA
pp. 101
Jestis Sanchez, Universitat Politbcnica de Catalunya
Antonio Gonzalez, Universitat Politbcnica de Catalunya
pp. 124
Accelerator Architecture
Javier Zalamea, Universitat Polithnica de Catalunya
Josep Llosa, Universitat Polithnica de Catalunya
Eduard Ayguade, Universitat Polithnica de Catalunya
Mateo Valero, Universitat Polithnica de Catalunya
pp. 137
Yuan Chou, Carnegie Mellon University
Pazhani Pillai, Carnegie Mellon University
Herman Schmit, Carnegie Mellon University
John Pau, Carnegie Mellon University
pp. 147
Ujval J. Kapasi, Stanford University
William J. Dally, Stanford University
Scott Rixner, Stanford University
Peter R. Mattson, Stanford University
John D. Owens, Stanford University
Brucek Khailany, Stanford University
pp. 159
F. Vermeulen, Katholieke Univ. Leuven
L. Nachtergaele, Katholieke Univ. Leuven
F. Catthoor, Katholieke Univ. Leuven
D. Verkest, Katholieke Univ. Leuven
H. De Man, Katholieke Univ. Leuven
pp. 171
Low-Power Design
J. Adam Butts, University of Wisconsin-Madison
Gurindar S. Sohi, University of Wisconsin-Madison
pp. 191
Micheal Huang, University Of Illinois at Urbana-Champaign
Jose Renau, University Of Illinois at Urbana-Champaign
Seung-Moon Yoo, University Of Illinois at Urbana-Champaign
Josep Torrellas, University Of Illinois at Urbana-Champaign
pp. 202
Michael Zhang, MIT Laboratory for Computer, Science
Krste Asanovie, MIT Laboratory for Computer, Science
pp. 214
Memory Hierarchy II
Amir Roth, Computer Sciences Department, University of Wisconsin
Gurindar S. Sohi, Computer Sciences Department, University of Wisconsin
pp. 223
Jun Yang, The University of Arizona, Tucson, AZ 85721
Youtao Zhang, The University of Arizona, Tucson, AZ 85721
Rajiv Gupta, The University of Arizona, Tucson, AZ 85721
pp. 258
Dynamic Translation and Multithreading
Sanjay J. Patel, University of Illinois at Urbana-Champaign
Tony Tung, University of Illinois at Urbana-Champaign
Satarupa Bose, University of Illinois at Urbana-Champaign
Matthew M. Crum, University of Illinois at Urbana-Champaign
pp. 303
Superscalar Architecture II
Joan-Manuel Parcerisa, Dept. d' Arquitectura de Computadors, Universitat Politecnica de Catalunya
Antonio Gonzalez, Dept. d' Arquitectura de Computadors, Universitat Politecnica de Catalunya
pp. 317
Author Index
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