Foreword

Committees (PDF)

pp. x

Reviewers (PDF)

pp. xii

Session 1: Welcome and Keynote: Chair: Uri Weiser, Intel

New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies (Abstract)

Fred J. Pollack, Intel Fellow

pp. 2

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Session 2: Faster FrontEnd: Chair: Gary Tyson, The University of Michigan, Ann Arbor

Control Independence in Trace Processors (Abstract)

Eric Rotenberg, North Carolina State University

Jim Smith, University of Wisconsin at Madison

pp. 4

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Fetch Directed Instruction Prefetching (Abstract)

Glenn Reinman, University of California at San Diego

Brad Calder, University of California at San Diego

Todd Austin, University of Michigan

pp. 16

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Improving Branch Predictors by Correlating on Data Values (Abstract)

Timothy H. Heil, University of Wisconsin at Madison

J.E. Smith, University of Wisconsin at Madison

Zak Smith, Hewlett-Packard

pp. 28

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Instruction Fetch Mechanisms for Multipath Execution Processors (Abstract)

Artur Klauser, University of Colorado at Boulder

Dirk Grunwald, University of Colorado at Boulder

pp. 38

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Session 3: 3D and MultiMedia: Chair: Matthew Farrens, University of California, Davis

A Superscalar 3D Graphics Engine (Abstract)

Andrew Wolfe, S3 Incorporated

Derek B. Noonburg, S3 Incorporated

pp. 50

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Dynamic 3D Graphics Workload Characterization and the Architectural Implications (Abstract)

Tulika Mitra, State University of New York at Stony Brook

Tzi-cker Chiueh, State University of New York at Stony Brook

pp. 62

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Exploiting a New Level of DLP in Multimedia Applications (Abstract)

Jesus Corbal, Universitat Polit?cnica de Catalunya

Mateo Valero, Universitat Polit?cnica de Catalunya

Roger Espasa, Compaq Computer Corporation

pp. 72

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Session 4: Efficient Embedded Processors: Chair: Kemal Ebcioglu, IBM

Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors (Abstract)

Sergei Y. Larin, North Carolina State University at Raleigh

Thomas M. Conte, North Carolina State University at Raleigh

pp. 82

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Evaluation of a High Performance Code Compression Method (Abstract)

Charles Lefurgy, University of Michigan

Eva Piccininni, University of Michigan

Trevor Mudge, University of Michigan

pp. 93

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Low-Cost Branch Folding for Embedded Applications with Small Tight Loops (Abstract)

Lea Hwang Lee, Motorola Incorporated

Jeff, Motorola Incorporated

Scott, Motorola Incorporated

Bill Moyer, Motorola Incorporated

John Arends, Motorola Incorporated

pp. 103

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Session 5: Memory Hierarchy: Chair: Doug Burger, University of Texas, Austin

Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems (Abstract)

Santosh G. Abraham, Hewlett-Packard Laboratories

Scott A. Mahlke, Hewlett-Packard Laboratories

pp. 114

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Hardware Identification of Cache Conflict Misses (Abstract)

Jamison D. Collins Dean M. Tullsen, University of California at San Diego

pp. 126

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Access Region Locality for High-Bandwidth Processor Memory System Design (Abstract)

Sangyeun Cho, Samsung Electronics Corporation

Pen-Chung Yew, University of Minnesota

Gyungho Lee, Iowa State University

pp. 136

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Code Transformations to Improve Memory Parallelism (Abstract)

Vijay S. Pai, Rice University

Sarita Adve, University of Illinois

pp. 147

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Session 6: Better Scheduling: Chair: Stephan Jourdan, Intel

Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results (Abstract)

Daniel A. Connors, University of Illinois at Urbana

Wen-mei W. Hwu, University of Illinois at Urbana

pp. 158

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Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing (Abstract)

Soner Onder, Michigan Technological University

Rajiv Gupta, The University of Arizona

pp. 170

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Read-After-Read Memory Dependence Prediction (Abstract)

Andreas Moshovos, Northwestern University

Gurindar S. Sohi, University of Wisconsin at Madison

pp. 177

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Delaying Physical Register Allocation through Virtual-Physical Registers (Abstract)

Teresa Monreal, Universitat Polit?cnica de Catalunya

Victor Viñals, Universitat Polit?cnica de Catalunya

Antonio González, University de Zaragoza

Mateo Valero, University de Zaragoza

José González, University de Zaragoza

pp. 186

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Session 7: Invited Speaker: Chair: Gabby Silberman, IBM, Canada

Core Technologies in Hardware and Software (Abstract)

Bruce Shriver

pp. 194

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Session 8: Novel Microarchitectures and Multithreading: Chair: Brad Calder, University of California, San Diego

DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design (Abstract)

Todd M. Austin, University of Michigan

pp. 196

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Exploiting ILP in Page-Based Intelligent Memory (Abstract)

Mark Oskin, University of California at Davis

Justin Hensley, University of California at Davis

Diana Keen, University of California at Davis

Frederic T. Chong, University of California at Davis

Matthew Farrens, University of California at Davis

Aneet Chopra, University of California at Davis

pp. 208

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The Use of Multithreading for Exception Handling (Abstract)

Craig B. Zilles, University of Wisconsin at Madison

Gurindar S. Sohi, University of Wisconsin at Madison

Joel S. Emer, Compaq Computer Corporation

pp. 219

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Value Prediction for Speculative Multithreaded Architectures (Abstract)

Pedro Marcuello, Universitat Polit?cnica de Catalunya

Jordi Tubella, Universitat Polit?cnica de Catalunya

Antonio González, Universitat Polit?cnica de Catalunya

pp. 230

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Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors (Abstract)

Session 9: Low Power Enhancements: Chair: Mateo Valero, Universitat Politecnica de Catalunya, Spain

Enric Musoll, XStream Logic Incorporated

pp. 238

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Selective Cache Ways: On-Demand Cache Resource Allocation (Abstract)

David H. Albonesi, University of Rochester

pp. 248

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Session 10: Compilers: Chair: David Bernstein, IBM, Israel

Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs (Abstract)

Jay Bharadwaj, Intel Corporation

Kishore Menezes, Intel Corporation

Chris McKinsey, Motorola Incorporated

pp. 262

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Balance Scheduling: Weighting Branch Tradeoffs in Superblocks (Abstract)

Alexandre E. Eichenberger, North Carolina State University

Waleed M. Meleis, Northeastern University

pp. 272

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Optimizations and Oracle Parallelism with Dynamic Translation (Abstract)

Kemal Ebcioglu, IBM Thomas J. Watson Research Center

Erik R. Altman, IBM Thomas J. Watson Research Center

Sumedh Sathaye, IBM Thomas J. Watson Research Center

Michael Gschwind, IBM Thomas J. Watson Research Center

pp. 284

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Session 11: Summary and Awards

Index of Authors (PDF)

pp. 299