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IWIA
2005
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)

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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)

Oahu, Hawaii

January 17-January 19

ISBN: 0-7695-2483-4

Table of Contents

Superscalar Processor with Multi-Bank Register File (Abstract)

Tetsuo Hironaka, Hiroshima City University

Moto Maeda, Hiroshima City University

Kazuya Tanigawa, Hiroshima City University

Tetsuya Sueyoshi, Hiroshima University

Kenichi Aoyama, Hiroshima University

Tetsushi Koide, Hiroshima University

Hans Juergen Mattausch, Hiroshima University

Tadashi Saito, Hiroshima City University

pp. 3-12

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Steering and Forwarding Techniques for Reducing Memory Communication on a Clustered Microarchitecture (Abstract)

Hidetsugu Irie, Japan Science and Technology Agency and University of Tokyo

Naoya Hattori, Hitachi, Ltd.

Masanori Takada, Hitachi, Ltd.

Naoya Hatta, University of Tokyo

Takashi Toyoshima, University of Tokyo

Suichi Sakai, University of Tokyo

pp. 13-18

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The Bimode++ Branch Predictor (Abstract)

Kenji Kise, University of Electro-Communications and Japan Science and Technology Agency

Takahiro Katagiri, University of Electro-Communications

Hiroki Honda, University of Electro-Communications

Toshitsugu Yuba, University of Electro-Communications

pp. 19-26

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On the Use of Bit Filters in Shared Nothing Partitioned Systems (Abstract)

Josep Aguilar-Saborit, Universitat Politecnica de Catalunya

Victor Muntes-Mulero, Universitat Politecnica de Catalunya

Calisto Zuzarte, IBM Toronto Lab.

Hebert Pereyra, IBM Toronto Lab.

Josep-L. Larriba-Pey, Universitat Politecnica de Catalunya

pp. 29-37

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Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs (Abstract)

José L. Ayala, Universidad Politécnica de Madrid

David Atienza, Universidad Complutense de Madrid

Marisa López-Vallejo, Universidad Politécnica de Madrid

J. M. Mendías, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

C. A. López-Barrio, Universidad Politécnica de Madrid

pp. 65-71

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Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface (Abstract)

Noboru Tanabe, Toshiba Corporation

Akira Kitamura, Keio University

Tomotaka Miyashiro, Keio University

Yasuo Miyabe, Keio University

Tohru Izawa, Keio University

Yoshihiro Hamada, Tokyo University of Agriculture and Technology

Hironori Nakajo, Tokyo University of Agriculture and Technology

Hideharu Amano, Keio University

pp. 119-127

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SIMD Optimization in COINS Compiler Infrastructure (Abstract)

Mitsugu Suzuki, University of Electro-Communications

Nobuhisa Fujinami, Sony Computer Entertainment Inc.

Takeaki Fukuoka, Kanrikogaku Kenkyusho, Ltd.

Tan Watanabe, University of Electro-Communications

Ikuo Nakata, Hosei University

pp. 131-140

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