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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface
Oahu, Hawaii
January 17-January 19
ISBN: 0-7695-2483-4
Noboru Tanabe, Toshiba Corporation
Akira Kitamura, Keio University
Tomotaka Miyashiro, Keio University
Yasuo Miyabe, Keio University
Tohru Izawa, Keio University
Yoshihiro Hamada, Tokyo University of Agriculture and Technology
Hironori Nakajo, Tokyo University of Agriculture and Technology
Hideharu Amano, Keio University
Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948 ?s. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.
Citation:
Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano, "Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface," iwia, pp.119-127, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05), 2005
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