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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface
Oahu, Hawaii
January 17-January 19
ISBN: 0-7695-2483-4
| ASCII Text | x | ||
| Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano, "Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface," Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on, pp. 119-127, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/IWIA.2005.38, author = {Noboru Tanabe and Akira Kitamura and Tomotaka Miyashiro and Yasuo Miyabe and Tohru Izawa and Yoshihiro Hamada and Hironori Nakajo and Hideharu Amano}, title = {Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface}, journal ={Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on}, volume = {0}, year = {2005}, issn = {1527-1366}, pages = {119-127}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWIA.2005.38}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on TI - Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface SN - 1527-1366 SP119 EP127 A1 - Noboru Tanabe, A1 - Akira Kitamura, A1 - Tomotaka Miyashiro, A1 - Yasuo Miyabe, A1 - Tohru Izawa, A1 - Yoshihiro Hamada, A1 - Hironori Nakajo, A1 - Hideharu Amano, PY - 2005 KW - null VL - 0 JA - Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWIA.2005.38
Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948 ?s. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.
Citation:
Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano, "Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface," iwia, pp.119-127, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05), 2005
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