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- IWIA
- 2004
- Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Maui, Hawaii
January 12-January 14
ISBN: 0-7695-2205-X
Table of Contents
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 | High Performance, Low-Power Architectures |
Marco A. Ram?rez, U.P.C., Barcelona Spain; National Polytechnic Institute, M?xico
pp. 2-9
Kenji Kise, The University of Electro-Communications; PRESTO, Japan Science and Technology Agency (JST)
Takahiro Katagiri, The University of Electro-Communications; PRESTO, Japan Science and Technology Agency (JST)
pp. 10-19
 | Parallel Processing |
 | Compilers |
 | Applications |
Kiyofumi Tanaka, Japan Advanced Institute of Science and Technology; PRESTO, Japan Science and Technology Agency
pp. 109-118
 | Threaded Architectures |
Norito Kato, Tokyo University of Agriculture and Technology, Japan
Mikiko Sato, Tokyo University of Agriculture and Technology, Japan
Koichi Sasada, Tokyo University of Agriculture and Technology, Japan
Mitaro Namiki, Tokyo University of Agriculture and Technology, Japan
pp. 139-147
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