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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01)
Maui, Hawaii
January 18-January 19
ISBN: 0-7695-1309-3
Table of Contents
Low-Power System Design
Cache-In-Memory (Abstract)
Jason T. Zawodny, Univ. of Notre Dame
Peter M. Kogge, Univ. of Notre Dame
pp. 0003
Dmitry Ponomarev, State University of New York, Binghamton
Gurhan Kucuk, State University of New York, Binghamton
Kanad Ghose, State University of New York, Binghamton
pp. 0016
Ana Azevedo, University of California, Irvine
Radu Comnea, University of California, Irvine
Ilya Issenin, University of California, Irvine
Rajesh Gupta, University of California, Irvine
Nikil Dutt, University of California, Irvine
Alex Nicolau, University of California, Irvine
Alex Veidenbaum, University of California, Irvine
pp. 0025
Memory Hierarchy
Hironori Nakajo, Tokyo University of Agriculture and Technology
Masaaki Ishii, Tokyo University of Agriculture and Technology
Junji Yamamoto, Real World Computing Partnership
Tomohiro Kudo, Real World Computing Partnership
Tomonori Yokoyama, Keio University
Jun-ichiro Tsuchiya, Keio University
Hideharu Amano, Keio University
pp. 0053
Compilers/Operating Systems
High-Performance Systems
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