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Innovative Architecture for Future Generation High-Performance Processors and Systems (2001)
Maui, HI, USA
Jan. 18, 2001 to Jan. 19, 2001
ISBN: 0-7695-1309-3
TABLE OF CONTENTS
Preface (PDF)
pp. vi
pp. vii
Low-Power System Design
Cache-In-Memory (Abstract)
Jason T. Zawodny , Univ. of Notre Dame
Peter M. Kogge , Univ. of Notre Dame
pp. 0003
Ana-Maria Badulescu , University of California, Irvine
Alexander Veidenbaum , University of California, Irvine
pp. 0012
Dmitry Ponomarev , State University of New York, Binghamton
Gurhan Kucuk , State University of New York, Binghamton
Kanad Ghose , State University of New York, Binghamton
pp. 0016
Ana Azevedo , University of California, Irvine
Radu Comnea , University of California, Irvine
Ilya Issenin , University of California, Irvine
Rajesh Gupta , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
Alex Veidenbaum , University of California, Irvine
pp. 0025
Memory Hierarchy
Gianfranco Bilardi , Universita di Padova
Enoch Peserico , Massachusetts Institute of Technology
pp. 0037
Gianfranco Bilardi , Universita di Padova
Kattamuri Ekanadham , T.J. Watson Research Center
Pratap Pattnaik , T.J. Watson Research Center
pp. 0045
Hironori Nakajo , Tokyo University of Agriculture and Technology
Masaaki Ishii , Tokyo University of Agriculture and Technology
Junji Yamamoto , Real World Computing Partnership
Tomohiro Kudo , Real World Computing Partnership
Tomonori Yokoyama , Keio University
Jun-ichiro Tsuchiya , Keio University
Hideharu Amano , Keio University
pp. 0053
Compilers/Operating Systems
Hiroshi Nakayama , Kyushu University
Takuya Tanabayashi , Kyushu University
Makoto Amamiya , Kyushu University
pp. 0073
High-Performance Systems
Mitsuo Yokokawa , Japan Atomic Energy Research Institute
pp. 0093
Takanori Matsuzaki , Kyushu University
Makoto Amamiya , Kyushu University
Hiroshi Tomiyasu , University of Tsukuba
pp. 0100
Author Index (PDF)
pp. 0109
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