About the Conference

Steering Committee (PDF)

pp. viii

Program Committee (PDF)

pp. viii

IVC-95 Best Paper Award Winner (PDF)

pp. ix

IVC-96 Best Paper Award Winner (PDF)

pp. x

Session 1: Simulation Architectures and Language Interfaces: Chair: Mike Baird, Sylvan Technology, Inc.

An architecture for a verilog hardware accelerator (Abstract)

C. Burns

pp. 2

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INCA: a next-generation architecture for simulation (Abstract)

J. Lawrence

C. Ussery

pp. 12

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The Verilog Procedural Interface for the Verilog Hardware Description Language (Abstract)

C. Dawson, Cadence Design Syst. Inc., San Jose, CA, USA

S.K. Pattanam, Cadence Design Syst. Inc., San Jose, CA, USA

D. Roberts, Cadence Design Syst. Inc., San Jose, CA, USA

pp. 17

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Faster Verilog simulations using a cycle based programming methodology (Abstract)

M. Becker

pp. 24

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Session 2: Tools and Methodology: Chair: Ron Munoz, Alcatel Network Systems

VIP: a Verilog Interpreter for Preprocessing (Abstract)

S. Mittra, WIPRO Infotech. Ltd., Bangalore, India

pp. 34

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On the use of Verilog HDL in the conversion of existing hardware designs to newer technology (Abstract)

D. Crate, Comput Group, Motorola Inc., USA

pp. 39

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Multi-methodology design: an experimental comparison (Abstract)

R. Prasad, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA

H. Kobayashi, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA

pp. 45

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Vstyle: a coding style analyzer for synthesizable Verilog (Abstract)

B. Gelinas, Data General Corp., USA

pp. 50

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Session 3: Simulation and Synthesis Techniques: Chair: Yatin Trivedi, SEVA Technologies, Inc.

Towards a formal model of hardware synthesized from Verilog (Abstract)

M. Arnold, Wyoming Univ., Laramie, WY, USA

A. Wallace, Wyoming Univ., Laramie, WY, USA

J. Cupal, Wyoming Univ., Laramie, WY, USA

J. Cowles, Wyoming Univ., Laramie, WY, USA

F. Engineer, Wyoming Univ., Laramie, WY, USA

pp. 60

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Synthesizing multi-phase HDL programs (Abstract)

Szu-Tsung Cheng, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

pp. 67

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A sockets-based implementation of hardware and software co-design (Abstract)

A. Herbert, Dept. of Res. & Dev., Credence Syst. Corp., Fremont, CA, USA

pp. 77

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LEAH: an introduction to behavioral abstraction and co-simulation using Perl and Verilog (Abstract)

B. Gelinas, Data General Corp., USA

K. Dorman, Data General Corp., USA

E. Mednick, Data General Corp., USA

pp. 81

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Session 4: Design Validation and Verification: Chair: Samir Palnitkar, Indus Consulting Services, Inc.

Formal verification-a viable alternative to simulation? (Abstract)

A. Nordstrom, Northern Telecom Electron. Ltd., Ottawa, Ont., Canada

pp. 90

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Addressing the systems-in-silicon verification challenge: a new approach to logic verification (Abstract)

S. Caplow, Cadence Design Syst. Inc., San Jose, CA, USA

M. Sottak, Cadence Design Syst. Inc., San Jose, CA, USA

D. Kelf, Cadence Design Syst. Inc., San Jose, CA, USA

pp. 96

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Hierarchical test coverage (Abstract)

A. Herbert, Dept. of Res. & Dev., Credence Syst. Corp., Freemont, CA, USA

pp. 101

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ASIC design validation in a system context (Abstract)

J. Bartlett, Sylvan Technol. Inc., USA

pp. 105

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Author Index (PDF)

pp. 113