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1996 IEEE International Verilog HDL Conference (IVC '96)
Santa Clara, CA
March 26-March 28
ISBN: 0-8186-7429-6
Table of Contents
Session 1: Simulation Architectures and Language Interfaces: Chair: Mike Baird, Sylvan Technology, Inc.
C. Dawson, Cadence Design Syst. Inc., San Jose, CA, USA
S.K. Pattanam, Cadence Design Syst. Inc., San Jose, CA, USA
D. Roberts, Cadence Design Syst. Inc., San Jose, CA, USA
pp. 17
Session 2: Tools and Methodology: Chair: Ron Munoz, Alcatel Network Systems
R. Prasad, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
H. Kobayashi, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 45
Session 3: Simulation and Synthesis Techniques: Chair: Yatin Trivedi, SEVA Technologies, Inc.
M. Arnold, Wyoming Univ., Laramie, WY, USA
A. Wallace, Wyoming Univ., Laramie, WY, USA
J. Cupal, Wyoming Univ., Laramie, WY, USA
J. Cowles, Wyoming Univ., Laramie, WY, USA
F. Engineer, Wyoming Univ., Laramie, WY, USA
pp. 60
Szu-Tsung Cheng, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 67
Session 4: Design Validation and Verification: Chair: Samir Palnitkar, Indus Consulting Services, Inc.
S. Caplow, Cadence Design Syst. Inc., San Jose, CA, USA
M. Sottak, Cadence Design Syst. Inc., San Jose, CA, USA
D. Kelf, Cadence Design Syst. Inc., San Jose, CA, USA
pp. 96
A. Herbert, Dept. of Res. & Dev., Credence Syst. Corp., Freemont, CA, USA
pp. 101
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