- I
- IVC
- 1996
- 1996 IEEE International Verilog HDL Conference (IVC '96)
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1996 IEEE International Verilog HDL Conference (IVC '96) Santa Clara, CA March 26-March 28 ISBN: 0-8186-7429-6 Table of Contents
 | Session 1: Simulation Architectures and Language Interfaces: Chair: Mike Baird, Sylvan Technology, Inc. |
C. Dawson, Cadence Design Syst. Inc., San Jose, CA, USA
D. Roberts, Cadence Design Syst. Inc., San Jose, CA, USA pp. 17
| Session 2: Tools and Methodology: Chair: Ron Munoz, Alcatel Network Systems |
S. Mittra, WIPRO Infotech. Ltd., Bangalore, India pp. 34
D. Crate, Comput Group, Motorola Inc., USA pp. 39
R. Prasad, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
H. Kobayashi, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA pp. 45
| Session 3: Simulation and Synthesis Techniques: Chair: Yatin Trivedi, SEVA Technologies, Inc. |
J. Cupal, Wyoming Univ., Laramie, WY, USA pp. 60
Szu-Tsung Cheng, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA pp. 67
A. Herbert, Dept. of Res. & Dev., Credence Syst. Corp., Fremont, CA, USA pp. 77
| Session 4: Design Validation and Verification: Chair: Samir Palnitkar, Indus Consulting Services, Inc. |
A. Nordstrom, Northern Telecom Electron. Ltd., Ottawa, Ont., Canada pp. 90
S. Caplow, Cadence Design Syst. Inc., San Jose, CA, USA
M. Sottak, Cadence Design Syst. Inc., San Jose, CA, USA
D. Kelf, Cadence Design Syst. Inc., San Jose, CA, USA pp. 96
A. Herbert, Dept. of Res. & Dev., Credence Syst. Corp., Freemont, CA, USA pp. 101 Usage of this product signifies your acceptance of the Terms of Use.
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