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Verilog HDL Conference, IEEE International (1995)
Santa Clara, CA
Mar. 27, 1995 to Mar. 29, 1995
ISBN: 0-8186-7082-7
TABLE OF CONTENTS
pp. viii
pp. viii
Session 1: Verification/Simulation: Chair: Michael Ciletti, University of Colorado
S. Palnitkar , Sun Microsystems Inc., Mountain View, CA, USA
D. Parham , Sun Microsystems Inc., Mountain View, CA, USA
pp. 2
G. York , Cadence Berkeley Lab., Cadence Design Syst. Inc., San Jose, CA, USA
R. Mueller-Thuns , Cadence Berkeley Lab., Cadence Design Syst. Inc., San Jose, CA, USA
J. Patel , Cadence Berkeley Lab., Cadence Design Syst. Inc., San Jose, CA, USA
D. Beatty , Cadence Berkeley Lab., Cadence Design Syst. Inc., San Jose, CA, USA
pp. 9
M.G. Arnold , Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
T.A. Bailey , Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
J.R. Cowles , Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
J.J. Cupal , Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
F.N. Engineer , Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
pp. 19
Chong Guan Tan , Chronologic Simulation, USA
pp. 29
Session 2: Top Down Design Methodology: Chair: Joseph Hoch, Compaq Computers:
Szu-Tsung Cheng , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
G. York , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
K. Yelick , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Saldanha , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 32
T. Yatani , Semicond. Co., Sony Corp., Atsugi, Japan
K. Sato , Semicond. Co., Sony Corp., Atsugi, Japan
M. Niizato , Semicond. Co., Sony Corp., Atsugi, Japan
pp. 40
M. Joshi , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
H. Kim , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
H. Kobayashi , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 44
K. Siomalas , Bell-Northern Res., Ottawa, Ont., Canada
pp. 49
Session 3: Designs: Chair: Mike Baird, Sylvan Technology
A. Shyamprakash , Cadence Design Syst. (India) Pvt. Ltd., Noida, India
C.P. Ravikumar , Cadence Design Syst. (India) Pvt. Ltd., Noida, India
pp. 58
J.C. Diaz , Telefonica Investigacion y Desarrollo, Madrid, Spain
P. Plaza , Telefonica Investigacion y Desarrollo, Madrid, Spain
L.A. Merayo , Telefonica Investigacion y Desarrollo, Madrid, Spain
P. Scarfone , Telefonica Investigacion y Desarrollo, Madrid, Spain
M. Zamboni , Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 67
C.D. Anyanwu , Brunel Univ., Uxbridge, UK
I.P. Jalowiecki , Brunel Univ., Uxbridge, UK
pp. 73
Session 4: Debugging: Chair: Susan Wong, Mitsubishi Electronics
B.T. Davis , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 90
Tsu-Hua Wang , Sun Microsystems Inc., Mountain View, CA, USA
Chong Guan Tan , Sun Microsystems Inc., Mountain View, CA, USA
pp. 99
Session 5: Modeling: Chair: Yatin Trivedi, SEVA Technologies, Inc.
D.R. Smith , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 106
S. Mittra , WIPRO Infotech Inc., USA
pp. 114
P.P. Jain , CAE Plus Inc., Austin, TX, USA
pp. 119
Author Index (PDF)
pp. 135
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