CSDL - Proceedings I

1998 IVC/VIUF Conference (PDF)

pp. ix

Steering Committee (PDF)

pp. x

Program Committee (PDF)

pp. xi

IVC 1998 Best Paper Award Winners (PDF)

pp. xii

VIUF 1998 Best Paper Award Winners (PDF)

pp. xiii

Session 1: Technology or Compiler Technology Directions: Chair: P. George, ACEO Technology, Inc.

1.1: Integrating of Verilog-HDL and VHDL Languages in the SMASH (tm) Mixed-signal Multi-level Simulator (Abstract)

P. Sauge

G. Thuau

pp. 2

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1.2: A Case Study of Compaq's Simulation Environment Migration to Windows NT (Abstract)

W.R. Stresau

pp. 7

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1.3: Incremental Compilation in the VCS Environment (Abstract)

pp. 14

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1.4: Transitioning to the New PLI Standard (Abstract)

S. Sutherland

pp. 20

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1.5: Implementing C Designs in Hardware: A Full-Featured ANSI C to RTL Verilog Compiler in Action (Abstract)

D. Soderman

Y. Panchul

pp. 22

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Session 2: Language Issues: Chair: S. Bailey, VeriBest, Inc.

2.1: A Procedural Language Interface for VHDL and Its Typical Applications (Abstract)

F. Martinolle

A. Sherer

pp. 32

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2.2: VHDL 200x - Requirements from Testbench-View (Abstract)

pp. 39

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2.3: Considerations on System-Level Behavioural and Structural Modeling Extensions to VHDL (Abstract)

P.J. Ashenden

P.A. Wilsey

pp. 42

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Session 3: Silicon Centric RTL: Chair: T. O'Connor, Avid Technology Inc.

3.1: Practical FSM Analysis for Verilog (Abstract)

T.-H. Wang

T. Edsall

pp. 52

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3.2: Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog (Abstract)

pp. 59

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3.3: Verilog Nonblocking Assignments Demystified (Abstract)

C.E. Cummings

pp. 67

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Session 4: System Level Design: Chair: D. Barton, Intermetrics, Inc.

4.1: Process-Level Modeling with VHDL (Abstract)

J. Armstrong

pp. 72

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4.2: Tools for Rapid Construction of VHDL Performance Models for DSP Systems (Abstract)

pp. 77

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4.3: Modeling Communication with Objective VHDL (Abstract)

Wolfram Putzke-R?ming

Martin Radetzki

Wolfgang Nebel

pp. 83

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4.4: Application of VHDL to Software Radio Technology (Abstract)

J. McCloskey

pp. 90

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Session 5: Customizing the Simulation Environment: Chair: B. Erickson, Compaq Computer Corp.

5.1: Verilog Plus C Language Modeling with PLI 2.0: The Next Generation Simulation Language (Abstract)

S. Meyer

pp. 98

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5.2: EP3: An Extensible Perl PreProcessor (Abstract)

G. Spivey

pp. 106

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5.3: A Mixed-Language Simulator for Concurrent Engineering (Abstract)

D.A. Burgoon

pp. 114

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5.4: A Strategy for C-Based Verification (Abstract)

P. Herman

pp. 120

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Session 6: Legacy and Reuse: Chair: L. Concha, United States Air Force

6.1: Reuse of Models and Testbenches at Different Levels of Abstraction (Abstract)

G.A. Frank

F.G. Gray

S. Gopalakrishnan

W. Song

pp. 130

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6.2: ModelMaker: A Tool for Rapid Modeling from Device Descriptions (Abstract)

W.R. Cyre

A. Gunawan

pp. 138

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6.3: Improving VHDL Soft-Cores Reuse with Software-like Reviews and Audits Procedures (Abstract)

A. Castellví S. Olco

M. García

pp. 143

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Session 7: Verification/Validation/Testbench Strategies: Chair: A. Herbert, IKOS Systems, Inc.

7.1: Overcoming the Limitations of Self-Checking Stimulus through the Use of an ASIC Mirror (Abstract)

R.D. Benson

pp. 148

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7.2: A Pseudorandom Test Environment (Abstract)

B. Wood

pp. 153

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7.3: Networked Object Oriented Verification with C++ and Verilog (Abstract)

pp. 158

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7.4: A Loosely Coupled C/Verilog Environment for System Level Verification (Abstract)

A.S. Meyer

pp. 165

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Session 8: Test, Timing, and Tools: Chair: J. Willis, FTL Systems, Inc.

8.1: A Functional Test Planning System for Validation of DSP Circuits Modeled in VHDL (Abstract)

pp. 172

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8.2: Scan Parallel Loading in VHDL (Abstract)

J.P. Vo

pp. 178

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8.3: STG Timing Extensions and Simulation (Abstract)

pp. 188

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8.4: SAVANT/TyVIS/WARPED: Components for the Analysis and Simulation of VHDL (Abstract)

pp. 195

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Author Index (PDF)

pp. 202