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Verilog HDL Conference and VHDL International Users Forum, IEEE International (1998)
Santa Clara, California
Mar. 16, 1998 to Mar. 19, 1998
ISBN: 0-8186-8415-1
TABLE OF CONTENTS
Preface (PDF)
pp. viii
Session 1: Technology or Compiler Technology Directions: Chair: P. George, ACEO Technology, Inc.
Session 2: Language Issues: Chair: S. Bailey, VeriBest, Inc.
Session 3: Silicon Centric RTL: Chair: T. O'Connor, Avid Technology Inc.
Session 4: System Level Design: Chair: D. Barton, Intermetrics, Inc.
Session 5: Customizing the Simulation Environment: Chair: B. Erickson, Compaq Computer Corp.
Session 6: Legacy and Reuse: Chair: L. Concha, United States Air Force
Session 7: Verification/Validation/Testbench Strategies: Chair: A. Herbert, IKOS Systems, Inc.
Session 8: Test, Timing, and Tools: Chair: J. Willis, FTL Systems, Inc.
Author Index (PDF)
pp. 202
20 ms
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