• I
  • IVC-VIUF
  • 1998
  • International Verilog HDL Conference and VHDL International Users Forum
Advanced Search 
International Verilog HDL Conference and VHDL International Users Forum
Santa Clara, California
March 16-March 19
ISBN: 0-8186-8415-1
Table of Contents
Preface (PDF)
pp. viii
Session 1: Technology or Compiler Technology Directions: Chair: P. George, ACEO Technology, Inc.
Session 2: Language Issues: Chair: S. Bailey, VeriBest, Inc.
Session 3: Silicon Centric RTL: Chair: T. O'Connor, Avid Technology Inc.
Session 4: System Level Design: Chair: D. Barton, Intermetrics, Inc.
Session 5: Customizing the Simulation Environment: Chair: B. Erickson, Compaq Computer Corp.
Session 6: Legacy and Reuse: Chair: L. Concha, United States Air Force
Session 7: Verification/Validation/Testbench Strategies: Chair: A. Herbert, IKOS Systems, Inc.
Session 8: Test, Timing, and Tools: Chair: J. Willis, FTL Systems, Inc.
Usage of this product signifies your acceptance of the Terms of Use.