M.-W. Lin, J.R. Armstrong, G.A. Frank, L. Concha, "8.1: A Functional Test Planning System for Validation of DSP Circuits Modeled in VHDL," Verilog HDL Conference and VHDL International Users Forum, IEEE International, pp. 172, International Verilog HDL Conference and VHDL International Users Forum, 1998.

@article{ 10.1109/IVC.1998.660698,
author = {M.-W. Lin and J.R. Armstrong and G.A. Frank and L. Concha},
title = {8.1: A Functional Test Planning System for Validation of DSP Circuits Modeled in VHDL},
journal ={Verilog HDL Conference and VHDL International Users Forum, IEEE International},
volume = {0},
year = {1998},
issn = {1085-9403},
pages = {172},
doi = {http://doi.ieeecomputersociety.org/10.1109/IVC.1998.660698},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - Verilog HDL Conference and VHDL International Users Forum, IEEE International
TI - 8.1: A Functional Test Planning System for Validation of DSP Circuits Modeled in VHDL
SN - 1085-9403
SP
EP
A1 - M.-W. Lin,
A1 - J.R. Armstrong,
A1 - G.A. Frank,
A1 - L. Concha,
PY - 1998
VL - 0
JA - Verilog HDL Conference and VHDL International Users Forum, IEEE International
ER -