Awards

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Real-time testing method for 16 Gbps 4-PAM signal interface (Abstract)

Masahiro Ishida, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Kiyotaka Ichiyama, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Daisuke Watanabe, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Masayuki Kawabata, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Toshiyuki Okayasu, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

pp. 1-10

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Integrated optimization of semiconductor manufacturing: A machine learning approach (Abstract)

Nathan Kupp, Department of Electrical Engineering, Yale University, New Haven, CT 06511

Yiorgos Makris, Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080

pp. 1-10

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Cell-aware Production test results from a 32-nm notebook processor (Abstract)

F. Hapke, Mentor Graphics Hamburg Germany

M. Reese, AMD, Inc., Austin, Texas, USA

J. Rivers, AMD, Inc., Austin, Texas, USA

A. Over, AMD, Inc., Austin, Texas, USA

V. Ravikumar, AMD, Pte Ltd. Singapore Singapore

W. Redemund, Mentor Graphics Hamburg Germany

A. Glowatz, Mentor Graphics Hamburg Germany

J. Schloeffel, Mentor Graphics Hamburg Germany

J. Rajski, Mentor Graphics, Wilsonville, Oregon, USA

pp. 1-9

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A dynamic programming solution for optimizing test delivery in multicore SOCs (Abstract)

Mukesh Agrawal, Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA

Michael Richter, Intel Mobile Communications, Am Campeon 10-12, 85579, Neubiberg, Germany

Krishnendu Chakrabarty, Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA

pp. 1-10

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On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing (Abstract)

Weichi Ding, Altera Corporation, San Jose, CA, USA

Mingde Pan, Altera Corporation, San Jose, CA, USA

Wilson Wong, Altera Corporation, San Jose, CA, USA

Daniel Chow, Altera Corporation, San Jose, CA, USA

Mike Peng Li, Altera Corporation, San Jose, CA, USA

Sergey Shumarayev, Altera Corporation, San Jose, CA, USA

pp. 1-7

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Adaptive test selection for post-silicon timing validation: A data mining approach (Abstract)

Ming Gao, Electrical and Computer Engineering Department, University of California, Santa Barbara, California 93106, U. S. A.

Peter Lisherness, Electrical and Computer Engineering Department, University of California, Santa Barbara, California 93106, U. S. A.

Kwang-Ting (Tim) Cheng, Electrical and Computer Engineering Department, University of California, Santa Barbara, California 93106, U. S. A.

pp. 1-7

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In-system constrained-random stimuli generation for post-silicon validation (Abstract)

Adam B. Kinsman, Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada

Ho Fai Ko, Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada

Nicola Nicolici, Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, L8S 4K1, Canada

pp. 1-10

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8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability (Abstract)

Shoji Kojima, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Yasuyuki Arai, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Tasuku Fujibe, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Tsuyoshi Ataka, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Atsushi Ono, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Ken-ichi Sawada, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Daisuke Watanabe, ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

pp. 1-9

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Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter (Abstract)

David C. Keezer, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA

Te-Hui Chen, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA

Carl E. Gray, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA

Hyun Woo Choi, Samsung Electronics Corp., Suwon, Korea

Sungyeol Kim, Samsung Electronics Corp., Suwon, Korea

Seongkwan Lee, Samsung Electronics Corp., Suwon, Korea

Hosun Yoo, Samsung Electronics Corp., Suwon, Korea

pp. 1-11

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Spatial estimation of wafer measurement parameters using Gaussian process models (Abstract)

Nathan Kupp, Department of Electrical Engineering, Yale University, New Haven, CT 06511

Ke Huang, Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080

John Carulli, Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX 75243

Yiorgos Makris, Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080

pp. 1-8

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Screening customer returns with multivariate test analysis (Abstract)

Nik Sumikawa, University of California, Santa Barbara

Jeff Tikkanen, University of California, Santa Barbara

Li-C. Wang, University of California, Santa Barbara

LeRoy Winemberg, Freescale Semiconductor, Inc

Magdy S. Abadir, Freescale Semiconductor, Inc

pp. 1-10

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On pinpoint capture power management in at-speed scan test generation (Abstract)

X. Wen, Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan

Y. Nishida, Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan

K. Miyase, Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan

S. Kajihara, Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan

P. Girard, LIRMM, 161 rue Ada, 34095 Montpellier, France

M. Tehranipoor, University of Connecticut, Storrs, CT 06296, USA

L.-T. Wang, SynTest Technologies, Inc., Sunnyvale, CA 94086, USA

pp. 1-10

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A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation (Abstract)

Yuta Yamato, Nara Institute of Science and Technology, Ikoma, Japan

Tomokazu Yoneda, Nara Institute of Science and Technology, Ikoma, Japan

Kazumi Hatayama, Nara Institute of Science and Technology, Ikoma, Japan

Michiko Inoue, Nara Institute of Science and Technology, Ikoma, Japan

pp. 1-8

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Functional test of small-delay faults using SAT and Craig interpolation (Abstract)

Matthias Sauer, Albert-Ludwigs-University Freiburg Georges-K¨ohler-Allee 051 79110 Freiburg, Germany

Stefan Kupferschmid, Albert-Ludwigs-University Freiburg Georges-K¨ohler-Allee 051 79110 Freiburg, Germany

Alexander Czutro, Albert-Ludwigs-University Freiburg Georges-K¨ohler-Allee 051 79110 Freiburg, Germany

Ilia Polian, University of Passau, Innstraße 43, 94032 Passau, Germany

Sudhakar Reddy, University of Iowa, 5324 Seamans Center, Iowa City, United States

Bernd Becker, Albert-Ludwigs-University Freiburg Georges-K¨ohler-Allee 051 79110 Freiburg, Germany

pp. 1-8

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An ATE architecture for implementing very high efficiency concurrent testing (Abstract)

Takahiro Nakajima, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Takeshi Yaguchi, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

Hajime Sugimura, Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan

pp. 1-10

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Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization (Abstract)

Nicholas Tzou, School of Electrical and Computer Engineering, Georgia Institute of Technology

Debesh Bhatta, School of Electrical and Computer Engineering, Georgia Institute of Technology

Sen-Wen Hsiao, School of Electrical and Computer Engineering, Georgia Institute of Technology

Hyun Woo Choi, School of Electrical and Computer Engineering, Georgia Institute of Technology

Abhijit Chatterjee, School of Electrical and Computer Engineering, Georgia Institute of Technology

pp. 1-10

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Power integrity control of ATE for emulating power supply fluctuations on customer environment (Abstract)

Masahiro Ishida, Advantest Corporation, Meiwa-machi, Gunma, 370-0718, Japan

Toru Nakura, VLSI Design and Education Center, the University of Tokyo, Tokyo, 113-0032, Japan

Toshiyuki Kikkawa, VLSI Design and Education Center, the University of Tokyo, Tokyo, 113-0032, Japan

Takashi Kusaka, Advantest Corporation, Meiwa-machi, Gunma, 370-0718, Japan

Satoshi Komatsu, VLSI Design and Education Center, the University of Tokyo, Tokyo, 113-0032, Japan

Kunihiro Asada, VLSI Design and Education Center, the University of Tokyo, Tokyo, 113-0032, Japan

pp. 1-10

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Event-driven framework for configurable runtime system observability for SOC designs (Abstract)

Jong Chul Lee, Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ

Faycel Kouteib, Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ

Roman Lysecky, Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ

pp. 1-10

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Modeling, verification and pattern generation for reconfigurable scan networks (Abstract)

Rafal Baranowski, ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany

Michael A. Kochte, ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany

Hans-Joachim Wunderlich, ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany

pp. 1-9

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Design validation of RTL circuits using evolutionary swarm intelligence (Abstract)

Min Li, Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA

Kelson Gent, Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA

Michael S. Hsiao, Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA

pp. 1-8

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Improving test compression by retaining non-pivot free variables in sequential linear decompressors (Abstract)

Sreenivaas S. Muthyala, Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712

Nur A. Touba, Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712

pp. 1-7

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Making predictive analog/RF alternate test strategy independent of training set size (Abstract)

Haithem Ayari, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Florence Azais, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Serge Bernard, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Mariane Comte, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Vincent Kerzerho, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Olivier Potin, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

Michel Renovell, LIRMM - CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Montpellier, France

pp. 1-9

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Calibration of a flexible high precision Power-On Reset during production test (Abstract)

Gerald Hilber, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria

Dominik Gruber, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria

Michael Sams, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria

Timm Ostermann, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria

pp. 1-7

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Root cause identification of an hard-to-find on-chip power supply coupling fail (Abstract)

Franco Stellari, IBM T.J. Watson Research Center, Yorktown Height, NY

Thomas Cowell, IBM System and Technology Group, Hopewell Junction, NY

Peilin Song, IBM T.J. Watson Research Center, Yorktown Height, NY

Michael Sorna, IBM System and Technology Group, Hopewell Junction, NY

Zeynep Toprak Deniz, IBM T.J. Watson Research Center, Yorktown Height, NY

John F. Bulzacchelli, IBM T.J. Watson Research Center, Yorktown Height, NY

Nandita A. Mitra, IBM System and Technology Group, Hopewell Junction, NY

pp. 1-7

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Improved volume diagnosis throughput using dynamic design partitioning (Abstract)

Xiaoxin Fan, Department of ECE University of Iowa Iowa City, IA 52242, USA

Huaxing Tang, Mentor Graphics, 8005 SW Boeckman RD, Wilsonville, OR 97070, USA

Yu Huang, Mentor Graphics, 8005 SW Boeckman RD, Wilsonville, OR 97070, USA

Wu-Tung Cheng, Mentor Graphics, 8005 SW Boeckman RD, Wilsonville, OR 97070, USA

Sudhakar M. Reddy, Department of ECE University of Iowa Iowa City, IA 52242, USA

Brady Benware, Mentor Graphics, 8005 SW Boeckman RD, Wilsonville, OR 97070, USA

pp. 1-10

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A unified method for parametric fault characterization of post-bond TSVs (Abstract)

Yu-Hsiang Lin, Electrical Engineering Department, National Tsing Hua University, Taiwan

Shi-Yu Huang, Electrical Engineering Department, National Tsing Hua University, Taiwan

Kun-Han (Hans) Tsai, Silicon Test Solutions, Mentor Graphics

Wu-Tung Cheng, Silicon Test Solutions, Mentor Graphics

Stephen Sunter, Silicon Test Solutions, Mentor Graphics

pp. 1-10

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Scan test of die logic in 3D ICs using TSV probing (Abstract)

Brandon Noia, Duke University, Dept. Electrical and Computer Engineering, Durham, NC 27708, USA

Shreepad Panth, Georgia Institute of Technology, Dept. Electrical and Computer Engineering, Atlanta, GA 30332, USA

Krishnendu Chakrabarty, Duke University, Dept. Electrical and Computer Engineering, Durham, NC 27708, USA

Sung Kyu Lim, Georgia Institute of Technology, Dept. Electrical and Computer Engineering, Atlanta, GA 30332, USA

pp. 1-8

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DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks (Abstract)

Sergej Deutsch, Cadence Design Systems, Munich, Germany

Brion Keller, Cadence Design Systems, Endicott, NY, USA

Vivek Chickermane, Cadence Design Systems, Endicott, NY, USA

Subhasish Mukherjee, Cadence Design Systems, Noida, India

Navdeep Sood, Cadence Design Systems, Noida, India

Sandeep Kumar Goel, TSMC, San Jose, CA, USA

Ji-Jan Chen, TSMC HsinChu, Taiwan

Ashok Mehta, TSMC, San Jose, CA, USA

Frank Lee, TSMC HsinChu, Taiwan

Erik Jan Marinissen, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

pp. 1-10

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FPGA-based synthetic instrumentation for board test (Abstract)

Igor Aleksejev, Testonica Lab OÜ, Tallinn, Estonia

Artur Jutman, Tallinn Univ. of Technology, Dept. of Comp. Engineering, Tallinn, Estonia

Sergei Devadze, Tallinn Univ. of Technology, Dept. of Comp. Engineering, Tallinn, Estonia

Sergei Odintsov, Testonica Lab OÜ, Tallinn, Estonia

Thomas Wenzel, Goepel Electronic GmbH, Jena, Germany

pp. 1-10

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Board assisted-BIST: Long and short term solutions for testpoint erosion — Reaching into the DFx toolbox (Abstract)

Zoe Conroy, Cisco Systems Inc., 170 West Tasman, Drive, San Jose, CA95134, USA

James Grealish, Intel® Corporation 5200 NE Elam Young, Parkway, Hillsboro, OR 97124, USA

Harrison Miles, Corelis, Inc., 13100 Alondra, Blvd, Cerritos, CA 90703, USA

Anthony J. Suto, Teradyne Inc., 700 Riverpark Drive, North Reading, MA 01864, USA

Alfred Crouch, Asset InterTech Inc, 2001 N. Central Expy, Richardson, TX 75080, USA

Skip Meyers, Hewlett Packard Co, 800 Foothills Blvd, Roseville, CA 95747, USA

pp. 1-10

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A memory yield improvement scheme combining built-in self-repair and error correction codes (Abstract)

Tze-Hsin Wu, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC

Po-Yuan Chen, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC

Mincent Lee, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC

Bin-Yen Lin, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC

Cheng-Wen Wu, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC

Chen-Hung Tien, Test Program Development Department, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan 30077, ROC

Hung-Chih Lin, Test Program Development Department, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan 30077, ROC

Hao Chen, Test Program Development Department, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan 30077, ROC

Ching-Nen Peng, Test Program Development Department, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan 30077, ROC

Min-Jer Wang, Test Program Development Department, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan 30077, ROC

pp. 1-9

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Testing strategies for a 9T sub-threshold SRAM (Abstract)

Hao-Yu Yang, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Chen-Wei Lin, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Hung-Hsin Chen, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Mango C.-T. Chao, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Ming-Hsien Tu, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Shyh-Jye Jou, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

Ching-Te Chuang, Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

pp. 1-10

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Low-power SRAMs power mode control logic: Failure analysis and test solutions (Abstract)

L. B. Zordan, LIRMM - Université Montpellier II / CNRS, Montpellier, France

A. Bosio, LIRMM - Université Montpellier II / CNRS, Montpellier, France

L. Dilillo, LIRMM - Université Montpellier II / CNRS, Montpellier, France

P. Girard, LIRMM - Université Montpellier II / CNRS, Montpellier, France

A. Todri, LIRMM - Université Montpellier II / CNRS, Montpellier, France

A. Virazel, LIRMM - Université Montpellier II / CNRS, Montpellier, France

N. Badereddine, Intel Mobile Communications, Sophia Antipolis, France

pp. 1-10

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A built-in self-test scheme for 3D RAMs (Abstract)

Yun-Chao Yu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Che-Wei Chou, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Jin-Fu Li, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Chih-Yen Lo, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Ding-Ming Kwai, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Yung-Fa Chou, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

Cheng-Wen Wu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320

pp. 1-9

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On-chip diagnosis for early-life and wear-out failures (Abstract)

Matthew Beckler, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

R. D. (Shawn) Blanton, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

pp. 1-10

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DART: Dependable VLSI test architecture and its implementation (Abstract)

Yasuo Sato, Kyushu Institute of Technology, Fukuoka, Japan

Seiji Kajihara, Kyushu Institute of Technology, Fukuoka, Japan

Tomokazu Yoneda, Nara Institute of Science and Technology, Nara, Japan

Kazumi Hatayama, Nara Institute of Science and Technology, Nara, Japan

Michiko Inoue, Nara Institute of Science and Technology, Nara, Japan

Yukiya Miura, Tokyo Metropolitan University, Tokyo, Japan

Satosni Untake, Oita University, Oita, Japan

Takumi Hasegawa, Hitachi Ltd., Information & Telecommunication Systems Company, Hardware MONOZUKURI Division, Tokyo, Japan

Motoyuki Sato, Hitachi Ltd., Information & Telecommunication Systems Company, Hardware MONOZUKURI Division, Tokyo, Japan

Kotaro Shimamura, Hitachi Ltd., Hitachi Research Laboratory, Ibaraki, Japan

pp. 1-10

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A design flow to maximize yield/area of physical devices via redundancy (Abstract)

Mohammad Mirza-Aghatabar, Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA

Melvin A. Breuer, Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA

Sandeep K. Gupta, Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA

pp. 1-10

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BS 1149.1 extensions for an online interconnect fault detection and recovery (Abstract)

Somayeh Sadeghi-Kohan, School of Electrical and Computer Engineering College of Engineering, University of Tehran, Iran

Majid Namaki-Shoushtari, School of Electrical and Computer Engineering College of Engineering, University of Tehran, Iran

Fatemeh Javaheri, School of Electrical and Computer Engineering College of Engineering, University of Tehran, Iran

Zainalabedin Navabi, School of Electrical and Computer Engineering College of Engineering, University of Tehran, Iran

pp. 1-9

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FALCON: Rapid statistical fault coverage estimation for complex designs (Abstract)

Shahrzad Mirkhani, Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712

Jacob A. Abraham, Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712

Toai Vo, Cisco Systems Inc., San Jose, CA 95134

Hongshin Jun, Cisco Systems Inc., San Jose, CA 95134

Bill Eklow, Cisco Systems Inc., San Jose, CA 95134

pp. 1-10

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Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit (Abstract)

A. Khare, Nvidia Graphics, Bangalore, India

P. Kishore, Nvidia Graphics, Bangalore, India

S. Reddy, Nvidia Graphics, Bangalore, India

K. Rajan, Nvidia Graphics, Bangalore, India

A. Sanghani, Nvidia Graphics, Santa Clara, United States

pp. 1-8

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Functional test content optimization for peak-power validation — An experimental study (Abstract)

Vinayak Kamath, University of California, Santa Barbara

Wen Chen, University of California, Santa Barbara

Nik Sumikawa, University of California, Santa Barbara

Li-C. Wang, University of California, Santa Barbara

pp. 1-10

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Experiences with non-intrusive sensors for RF built-in test (Abstract)

Louay Abdallah, TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France

Haralampos-G. Stratigopoulos, TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France

Salvador Mir, TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France

Christophe Kelma, NXP Semiconductors, 2 esplanade Anton Philips, Campus Effiscience, Colombelles BP20000, 14906 Caen, France

pp. 1-8

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A frequency measurement BIST implementation targeting gigahertz application (Abstract)

Matthieu Dubois, CEA-LETI - Grenoble - France

Emeric De Foucauld, CEA-LETI - Grenoble - France

Christopher Mounet, CEA-LETI - Grenoble - France

Serigne Dia, Presto Engineering - Grenoble - France

Cedric Mayor, Presto Engineering - Grenoble - France

pp. 1-8

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DC temperature measurements for power gain monitoring in RF power amplifiers (Abstract)

Josep Altet, Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain

Diego Mateo, Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain

Didac Gomez, Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain

Xavier Perpina, Centro Nacional de Microelectrónica, Bellaterra, Spain

Miquel Vellvehi, Centro Nacional de Microelectrónica, Bellaterra, Spain

Xavier Jorda, Centro Nacional de Microelectrónica, Bellaterra, Spain

pp. 1-8

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Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction (Abstract)

Motoo Ueda, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

Shinichi Ishikawa, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

Masaru Goishi, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

Satoru Kitagawa, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

Hiroshi Araki, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

Shuichi Inage, ADVANTEST Corporation 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan

pp. 1-7

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Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements (Abstract)

Xiaoxiao Wang, Freescale Semiconductor

Dat Tran, Freescale Semiconductor

Saji George, Freescale Semiconductor

LeRoy Winemberg, Freescale Semiconductor

Nisar Ahmed, Freescale Semiconductor

Steve Palosh, Freescale Semiconductor

Allan Dobin, Freescale Semiconductor

Mohammad Tehranipoor, ECE Department, University of Connecticut

pp. 1-9

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