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Austin, TX, USA
Nov. 8, 2005 to Nov. 8, 2005
ISBN: 0-7803-9038-5
pp: 8 pp.-273
J. Rearick , Agilent Technol., Fort Collins, CO, USA
ABSTRACT
Delay fault testing via AC scan is shown to suffer from test application problems that, if not accounted for, will cause a reduction in test quality. The problem of clock period stretching is demonstrated, and a novel circuit for calibrating this effect is described. Guidelines for AC scan test application on the tester to improve the quality of AC scan tests are presented, along with results from several large ASICs.
INDEX TERMS
clock period stretching, clock stretch calibration, AC scan testing, delay fault testing
CITATION
J. Rearick, "Calibrating clock stretch during AC scan testing", ITC, 2005, 2013 IEEE International Test Conference (ITC), 2013 IEEE International Test Conference (ITC) 2005, pp. 8 pp.-273, doi:10.1109/TEST.2005.1583984
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