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2013 IEEE International Test Conference (ITC) (2004)
Charlotte, NC, USA
Oct. 26, 2004 to Oct. 28, 2004
ISBN: 0-7803-8581-0
TABLE OF CONTENTS
Cover
Introduction
SESSION 1: PLENARY
SESSION 2: MICROPROCESSOR TEST
Benoit Provost , Intel Corporation. Hillsboro, OR, USA
Chee How Lim , Intel Corporation. Hillsboro, OR, USA
Mo Bashir , Intel Corporation. Hillsboro, OR, USA
Ali Muhtaroglu , Intel Corporation. Hillsboro, OR, USA
Tiffany Huang , Intel Corporation. Santa Clara, CA, USA
Kathy Tian , Intel Corporation. Santa Clara, CA, USA
Mubeen Atha , Intel Corporation. Santa Clara, CA, USA
Cangsang Zhao , Intel Corporation. Santa Clara, CA, USA
Harry Muljono , Intel Corporation. Santa Clara, CA, USA
pp. 23-30
M. Abadir , Freescale Semiconductor Inc., Austin, TX
A. Kolhatkar , Freescale Semiconductor Inc., Austin, TX
G. Vandling , Cadence Design Systems, Endicott, NY
L. Wang , University of California, Santa Barbara, CA
J. Abraham , University of Texas at Austin, Austin, TX
pp. 31-37
Mike Lin , Intel Corporation
Madhukar Reddy , Intel Corporation
Talal Jaber , Intel Corporation
Anil Sabbavarapu , Intel Corporation
Larry Thatcher , Intel Corporation
pp. 38-47
SESSION 3: LOGIC BIST
Hans-Joachim Wunderlich , Universitat Stuttgart, Germany
Valentin Gherman , Universitat Stuttgart, Germany
Friedrich Hapke , Philips Semiconductors, Germany
Michael Wittke , Philips Semiconductors, Germany
Michael Garbers , Philips Semiconductors, Germany
pp. 48-56
Janak H. Patel , University of Illinois at Urbana-Champaign
Thomas Rinderknecht , Mentor Graphics Corp., OR
Wu-Tung Cheng , Mentor Graphics Corp., OR
pp. 57-66
SESSION 4: BIST FOR JITTER
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Kiyotaka Ichiyama , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , University of Washington, Seattle, WA
Krawinkel Christian , Advantest Corporation, Gunma, Japan
Katsuaki Ohsawa , Advantest Corporation, Gunma, Japan
Masao Sugai , Advantest Corporation, Gunma, Japan
pp. 77-84
Bryan Nelson , University of Washington, Seattle, WA
Alan Chong , University of Washington, Seattle, WA
Hieu Nguyen , University of Washington, Seattle, WA
Karen Taylor , University of Washington, Seattle, WA
Mani Soma , University of Washington, Seattle, WA
Hosam Haggag , Santa Clara Design Center, National Semiconductor, Santa Clara, CA
Jeff Huard , Tacoma Design Center, National Semiconductor, Federal Way, WA
Jim Braatz , Tacoma Design Center, National Semiconductor, Federal Way, WA
pp. 85-94
Stephen Sunter , LogicVision, Inc.
J-F Cote , LogicVision, Inc.
pp. 95-104
SESSION 5: MEMORY TESTING
Benjamin M. Mauck , Intel Corporation, Hillsboro, OR, USA
Usman Azeez Mughal , Intel Corporation, Hillsboro, OR, USA
pp. 105-113
Ad J. Van de Goor , Delft University of Technology, Netherlands
Said Hamdioui , Philips Semiconductor R&D, France
Rob Wadsworth , ST Microlelctronics, Carrollton, TX
pp. 114-123
Rei-Fu Huang , National Tsing Hua University Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University Hsinchu, Taiwan
Chien-Chung Hung , Industrial Technology Research Institute Hsinchu, Taiwan
Ming-Jer Kao , Industrial Technology Research Institute Hsinchu, Taiwan
Yeong-Jar Chang , SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan
Wen-Ching Wu , SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan
pp. 124-133
SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS
Keith A. Jenkins , IBM T.J. Watson Research Center, NY
Stas Polonsky , IBM T.J. Watson Research Center, NY
Shinho Cho , Silla University, S. Korea
pp. 134-139
Peilin Song , IBM T.J. Watson Research Center, Yorktown Heights, NY
Franco Stellari , IBM T.J. Watson Research Center, Yorktown Heights, NY
Alan J. Weger , IBM T.J. Watson Research Center, Yorktown Heights, NY
Tian Xia , University of Vermont, Burlington, VT
pp. 140-147
John Carulli , Texas Instruments Inc.
Vijay Reddy , Texas Instruments Inc.
William Bosch , Texas Instruments Inc., Stafford, TX
Brendan Burgess , Texas Instruments Inc., Stafford, TX
pp. 148-155
SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE
Heon C. Kim , Cisco Systems, Inc.
Xinli Gu , Cisco Systems, Inc.
Sung S. Chung , Cisco Systems, Inc.
pp. 156-162
Sung S. Chung , Cisco Systems, Inc., Tasman Drive San Jose, CA
Hong-Shin Jun , Cisco Systems, Inc., Tasman Drive San Jose, CA
pp. 173-180
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST
Manu Rehani , LSI Logic Corporation
David Abercrombie , LSI Logic Corporation
Robert Madge , LSI Logic Corporation
Jim Teisher , LSI Logic Corporation
Jason Saw , Invantest Corporation, San Jose, CA, USA
pp. 181-189
Jonathan Hops , Semiconductor Test, Teradyne Inc., Boston, MA
Brian Phelps , Semiconductor Test, Teradyne Inc., Boston, MA
Bruce Sudweeks , Semiconductor Test, Teradyne Inc., Boston, MA
John Pane , Semiconductor Test, Teradyne Inc., Boston, MA
James Kinslow , Semiconductor Test, Teradyne Inc., Boston, MA
pp. 190-196
Peter Patten , Agilent Technologies, Germany
pp. 197-202
Robert Madge , LSI Logic Corporation, Gresham, Oregon
Brady Benware , LSI Logic Corporation, Ft. Collins, Colorado
Ritesh Turakhia , LSI Logic Corporation, Ft. Collins, Colorado
Robert Daasch , Portland State University, Portland, Oregon
Chris Schuermyer , Portland State University, Portland, Oregon
Jens Ruffler , Portland State University, Portland, Oregon
pp. 203-212
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS
Ananta K. Majhi , Philips Research, Netherlands
Guido Gronthoud , Philips Research, Netherlands
Stefan Eichenberger , Philips Semiconductor, Netherlands
pp. 213-222
Jing Wang , Texas A&M University, College Station, TX
D. M. H. Walker , Texas A&M University, College Station, TX
Divya Reddy , Texas Instruments, Inc.
Zhuo Li , Dept. of Electrical Engineering, Texas A&M University, College Station, TX
Weiping Shi , Dept. of Electrical Engineering, Texas A&M University, College Station, TX
Hari Balachandran , Texas Instruments, Inc.
pp. 223-231
Saravanan Padmanaban , Intel Corporation, Hillsboro, OR
pp. 232-241
Haihua Yan , Auburn University, Auburn, AL
Adit D. Singh , Auburn University, Auburn, AL
pp. 242-251
SESSION 10: MIXED-SIGNAL BIST AND DFT
Ashwin Raghunathan , University of Texas at Austin, TX
Ji Hwan Chun , University of Texas at Austin, TX
Jacob A. Abraham , University of Texas at Austin, TX
Abhijit Chatterjee , Georgia Institute of Technology
pp. 252-261
Abhishek Singh , University of Maryland, Baltimore County
Jim Plusquellic , University of Maryland, Baltimore County
pp. 262-270
Charles Stroud , Auburn University, Auburn, AL
Foster Dai , Auburn University, Auburn, AL
Shuying Qi , Auburn University, Auburn, AL
pp. 271-280
Geert Seuren , Philips Research Electronics Design, Netherlands
Tom Waayers , Philips Research Electronics Design, Netherlands
pp. 281-289
SESSION 11: ADVANCES IN TESTING FOR DEFECTS
Bram Kruseman , Philips Research Laboratories, Netherlands
Camelia Hora , Philips Research Laboratories, Netherlands
Stefan Eichenberger , Philips Semiconductors, Netherlands
Johan Meirlevede , Philips Semiconductors, Netherlands
pp. 290-299
J. Ruffler , LSI Logic Corporation, Gresham, OR
C. Schuermyer , LSI Logic Corporation, Gresham, OR
pp. 300-308
Chintan Patel , University of Maryland, Baltimore, MD
Abhishek Singh , University of Maryland, Baltimore, MD
Jim Plusquellic , University of Maryland, Baltimore, MD
pp. 319-328
SESSION 12: ADVANCES IN DFT
Matthew L. King , University of Wisconsin - Madison
Kewal K. Saluja , University of Wisconsin - Madison
pp. 329-338
Bo Yang , Polytechnic University, Brooklyn, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
Ramesh Karri , Polytechnic University, Brooklyn, NY
pp. 339-344
C. P. Ravikumar , Texas Instrument (India)
G. Hetherington , Texas Instrument Ltd, United Kingdom
pp. 345-354
Jayashree Saxena , Texas Instruments Inc., Dallas
Tony Fryars , Texas Instruments Inc., Dallas
Kenneth M. Butler , Texas Instruments Inc., Dallas
pp. 355-364
SESSION 13: BOARD AND SYSTEM TEST: BOARD TEST EFFECTIVENESS
Kenneth P. Parker , Agilent Technologies, Loveland, CO
pp. 365-374
D.C.L. Van Geest , Philips Research, Netherlands
A. Kumar , Indian Institute of Technology, Delhi, India
pp. 375-383
Carlos Michel , Hewlett-Packard Company, Jalisco, Mexico
Rosa D. Reinosa , Hewlett-Packard Company, Palo Alto, California, USA
pp. 384-392
SESSION 14: DEVELOPMENTS IN ATE SOFTWARE STANDARDS
Rochit Rajsuman , Advantest America Corporation
pp. 403-412
Ramachandran Krishnaswamy , Advantest America R&D Center Inc., Santa Clara, CA
Mark Elston , Advantest America R&D Center Inc., Santa Clara, CA
Toshiaki Adachi , Advantest America R&D Center Inc., Santa Clara, CA
Harsanjeet Singh , Advantest America R&D Center Inc., Santa Clara, CA
Bruce Parnas , Advantest America R&D Center Inc., Santa Clara, CA
pp. 413-422
Ernie Wahl , Agere Systems Allentown, PA. USA
David Dowding , Agilent Technologies, Inc. Loveland, CO. USA
pp. 423-431
SESSION 15: HANDLING OF UNKNOWNS
Subhasish Mitra , Intel Corporation Folsom, CA
Steven S. Lumetta , Univ. of Illinois, Urbana-Champaign
Michael Mitzenmacher , Harvard University
pp. 432-441
Hans-Joachim Wunderlich , University of Stuttgart, Germany
Harald Vranken , Philips Research Laboratories, The Netherlands
Friedrich Hapke , Philips Semiconductors GmbH, Hamburg, Germany
Michael Wittke , Philips Semiconductors GmbH, Hamburg, Germany
Piet Engelke , Albert-Ludwigs-University, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 442-451
Vivek Chickermane , Cadence Design Systems, Endicott, NY, USA
Brian Foutz , Cadence Design Systems, Endicott, NY, USA
Brion Keller , Cadence Design Systems, Endicott, NY, USA
pp. 452-461
SESSION 16: EMERGING TECHNOLOGIES FAULT MODELING and TOLERANCE
Jason G. Brown , Carnegie Mellon University, Pittsburgh PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh PA
pp. 462-471
Wenjing Rao , UC San Diego
Alex Orailoglu , UC San Diego
Ramesh Karri , India Polytechnic University, India
pp. 472-478
Jing Huang , Northeastern University Boston, MA
Fabrizio Lombardi , Northeastern University Boston, MA
pp. 479-488
SESSION 17: ADVANCES IN DIAGNOSIS
Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City, IA
pp. 489-497
Grzegorz Mrugalski , Mentor Graphics Corporation, Wilsonville, OR
Chen Wang , Mentor Graphics Corporation, Wilsonville, OR
Artur Pogiel , Poznan University of Technology, Poland
Jerzy Tyszer , Poznan University of Technology, Poland
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 498-507
T. Zanon , Carnegie Mellon University, Pittsburgh, PA
R. Desineni , Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
W. Maly , Carnegie Mellon University, Pittsburgh, PA
J. G. Brown , Carnegie Mellon University, Pittsburgh, PA
J. E. Nelson , Carnegie Mellon University, Pittsburgh, PA
Y. Fei , Carnegie Mellon University, Pittsburgh, PA
X. Huang , Carnegie Mellon University, Pittsburgh, PA
P. Gopalakrishnan , Carnegie Mellon University, Pittsburgh, PA
T. Vogels , Carnegie Mellon University, Pittsburgh, PA
V. Rovner , Carnegie Mellon University, Pittsburgh, PA
S. Tiwary , Carnegie Mellon University, Pittsburgh, PA
pp. 508-517
SESSION 18: TEST ECONOMICS
Brion Keller , Cadence Design Systems, Inc Endicott, NY
Thomas Bartenstein , Cadence Design Systems, Inc Endicott, NY
Vivek Chickermane , Cadence Design Systems, Inc Endicott, NY
pp. 518-524
Cyndee Wang , Cisco Systems, Inc., San Jose, CA
Abby Lee , Cisco Systems, Inc., San Jose, CA
Bill Eklow , Cisco Systems, Inc., San Jose, CA
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Jan A. Tofte , Mentor Graphics Corporation, Wilsonville, OR
Xinli Gu , Cisco Systems, Inc., San Jose, CA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 525-533
Pamela Gillis , IBM Corporation Essex Junction, VT
Andrew Ferko , IBM Corporation Essex Junction, VT
Kevin McCauley , Cadence Design Systems Endicott, NY
pp. 534-542
SESSION 19: BOARD AND SYSTEM TEST: EXTENDING BOUNDARY-SCAN TO RF AND HS SERIAL TESTING
Saghir A Shaikh , Intel Corporation, San Diego, CA
pp. 543-550
Juha Hakkinen , Electrical and Information Engineering, Electronics Laboratory, University of Oulu, Finland
Juha-Veikko Voutilainen , Optoelectronics and Measurement Techniques Laboratory, University of Oulu, Finland
Markku Moilanen , Optoelectronics and Measurement Techniques Laboratory, University of Oulu, Finland
pp. 551-559
Sylvia Patterson , Agilent Technologies ASIC Product Division Fort Collins, CO
Jeff Rearick , Agilent Technologies ASIC Product Division Fort Collins, CO
pp. 560-566
SESSION 20: SQUEEZING THE PICOSECONDS
Masashi Shimanouchi , Credence Systems, Baytech Drive, San Jose, CA
pp. 567-576
Ahmed Rashid Syed , Credence Systems Corporation, Baytech Dr. San Jose, CA
pp. 577-586
A.T. Sivaram , Credence Inc Intel, Baytech Drive, San Jose, CA
Pascal Pierra , Credence Inc Intel, Baytech Drive, San Jose, CA
Shida Sheibani , Credence Inc Intel, Baytech Drive, San Jose, CA
Nancy Wang-Lee , Intel Corporation, Chandler, AZ
Jorge E. Solorzano , Intel Corporation, Chandler, AZ
Lily Tran , Intel Corporation, Chandler, AZ
pp. 587-596
SESSION 21: ATPG/FAULT SIMULATION SPECIALTIES
Feng Shi , Yale University New Haven, CT
pp. 597-606
Junwu Zhang , Rutgers University, Piscataway, NJ
Vishwani D. Agrawal , Auburn University, AL
pp. 617-626
SESSION 22: INTERCONNECT TESTING AND FAULT DIAGNOSIS IN FPGAS
Dave Mark , xilinx.com Logic Dr. San Jose, CA
Jenny Fan , xilinx.com Logic Dr. San Jose, CA
pp. 627-634
Mehdi Baradaran Tahoori , Northeastern University Boston, MA
Subhasish Mitra , Intel Corporation Sacramento, CA
pp. 635-644
Mehdi Baradaran Tahoori , Northeastern University Boston, MA
pp. 645-654
SESSION 23: INDUSTRY CASE STUDIES IN TESTING
A. Cabbibo , LSI Logic Corporation, Gresham, Oregon
J. Conder , LSI Logic Corporation, Gresham, Oregon
M. Jacobs , LSI Logic Corporation, Gresham, Oregon
pp. 655-660
Leendert M. Huisman , IBM Microelectronics, Essex Junction, VT
Leah Pastel , IBM Microelectronics, Essex Junction, VT
pp. 661-668
Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
M. Enamul Amyeen , Intel Corporation, Hillsboro, OR
Sangbong Lee , Intel Corporation, Hillsboro, OR
pp. 669-678
SESSION 24: LECTURE SERIES - TEST TRENDS AND CHALLENGES
Sandip Kundu , Design Technology, Intel Corporation
T. M. Mak , Design Technology, Intel Corporation
Rajesh Galivanche , Design Technology, Intel Corporation
pp. 679-687
Camelia Hora , Philips Research Laboratories, Netherlands
Bram Kruseman , Philips Research Laboratories, Netherlands
Erik Jan Marinissen , Philips Research Laboratories, Netherlands
Robert Van Rijsinge , Philips Semiconductors - ATO, Nijmegen, Netherlands
pp. 688-697
Alfred L. Crouch , Chief Scientist, Inovys Corporation
pp. 698-703
SESSION 25: BOARD AND SYSTEM TEST: SYSTEM AND FIELD TEST
Anoosh Hosseini , Cisco Systems Inc., San Jose CA,
Chi Khuong , Cisco Systems Inc., San Jose CA,
Shyam Pullela , Cisco Systems Inc., San Jose CA
Toai Vo , Cisco Systems Inc., San Jose CA
Hien Chau , Cisco Systems Inc., San Jose CA
pp. 704-710
Paul J. Wheatley , Lucent Technologies, Holmdel, NJ
Kenneth Y. Ho , Lucent Technologies, Whippany, NJ
Ken L. Cheung , Lucent Technologies, Whippany, NJ
pp. 711-718
Yujun Zhang , Chinese Academy of Sciences. Beijing, China
pp. 719-727
SESSION 26: ATE FOR THE FASTEST DEVICES
Mohamed M. Hafed , DFT MicroSystems Canada Inc.
Geoffrey Duerden , DFT MicroSystems Canada Inc.
Bardia Pishdad , DFT MicroSystems Canada Inc.
Clarence Tam , DFT MicroSystems Canada Inc.
Sebastien Laberge , DFT MicroSystems Canada Inc.
Gordon W. Roberts , DFT MicroSystems Canada Inc.
pp. 728-737
Masashi Shimanouchi , Credence Inc Baytech Drive, San Jose, CA
Howard Maassen , Credence Inc Baytech Drive, San Jose, CA
A.T. Sivaram , Credence Inc Baytech Drive, San Jose, CA
pp. 738-747
D.C. Keezer , Georgia Institute of Technology
D. Minier , IBM Canada
F. Binette , IBM Canada
pp. 748-757
SESSION 27: SOC: MIXED SIGNALS, SIZE AND SPEED
Hans T. Heineken , Ample Communications Inc. Sacramento, CA
pp. 758-763
SESSION 28: RF TESTING
Erkan Acar , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
pp. 783-792
John Ferrario , IBM Corporation Essex Junction, VT, USA
Dana Brown , IBM Corporation Essex Junction, VT, USA
Jing Li , IBM Corporation Essex Junction, VT, USA
Jayendra Bhagat , IBM Corporation Essex Junction, VT, USA
pp. 793-800
Soumendu Bhattacharya , Georgia Institute of Technology, Atlanta, GA
pp. 801-809
ESSION 29: STATE SPACE EXPLORATION AND TEST GENERATION
Vijay K. Garg , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
Alper Sen , The University of Texas at Austin
pp. 810-819
Qingwei Wu , Virginia Tech, Blacksburg, VA
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 820-829
Geeng-Wei Lee , National Chiao Tung University, Hsinchu, Taiwan
Juinn-Dar Huang , National Chiao Tung University, Hsinchu, Taiwan
Jing-Yang Jou , National Chiao Tung University, Hsinchu, Taiwan
Chun-Yao Wang , National Chiao Tung University, Hsinchu, Taiwan
pp. 830-836
SESSION 30: SOC TEST CASE STUDIES
Charles Stroud , Auburn University, Alabama USA
Srinivas Garimella , Auburn University, Alabama USA
Jonathan Harris , Auburn University, Alabama USA
pp. 837-846
Moe Villalba , Plexus Design Solutions, Inc., Sudbury, MA
Richard Fisette , Mentor Graphics Corporation, Waltham, MA
pp. 847-856
SESSION 31: BOARD AND SYSTEM TEST: BOARD AND SYSTEM-LEVEL BIST TECHNIQUES
Szilard Enyedi , Department of Automation , Technical University of Cluj-Napoca, Romania
Gavril Toderean , Department of Telecommunications,Technical University of Cluj-Napoca, Romania
Alfredo Benso , Politecnico di Torino, Italy
Liviu Miclea , Department of Automation , Technical University of Cluj-Napoca, Romania
pp. 867-874
David Resnick , Cray Inc., Chippewa Falls, WI
pp. 875-882
SESSION 32: TEST OF DIGITAL, ANALOG AND MEMS C
A. Jr. Andrade , DELET-UFRGS, Univ. Fed. do Rio Grande do Sul Porto Alegre, Brazil
F. Azais , Universite de Montpellier II Montpellier Cedex 5, France
M. Renovell , Universite de Montpellier II Montpellier Cedex 5, France
M. Lubaszewski , IMSE-CNM Inst. de Microelectr. De Sevilla Sevilla, Spain
pp. 893-902
Benoit Provost , Intel Corporation, Logic Technology Development, Hillsboro, OR
Ali Muhtaroglu , Intel Corporation, Logic Technology Development, Hillsboro, OR
Greg Taylor , Intel Corporation, Logic Technology Development, Hillsboro, OR
pp. 903-906
Sreejit Chakravarty , Intel Corporation, Santa Clara, USA
Eric N Tran , Intel Corporation, Santa Clara, USA
pp. 907-915
SESSION 33: TEST COMPRESSION
Laung-Terng Wang , SynTest Technologies, Inc., Sunnyvale , CA
Khader S. Abdel-Hafez , SynTest Technologies, Inc., Sunnyvale , CA
Shianling Wu , SynTest Technologies, Inc., Sunnyvale , CA
Xiaoqing Wen , Kyushu Institute of Technology, Japan
Hiroshi Furukawa , NEC Micro Systems, Ltd., Japan
Fei-Sheng Hsu , SynTest Technologies, Inc., Taiwan
Shyh-Horng Lin , SynTest Technologies, Inc., Taiwan
Sen-Wei Tsai , SynTest Technologies, Inc., Taiwan
pp. 916-925
Christofer S. Tautermann , University of Innsbruck, Austria
Armin Wurtenberger , University of Innsbruck, Austria
pp. 926-935
Kedarnath J. Balakrishnan , University of Texas, Austin, TX
Nur A. Touba , University of Texas, Austin, TX
pp. 936-944
Baris Arslan , University of California, San Diego
pp. 945-952
SESSION 34: MIXED-SIGNAL TEST TECHNIQUES
Claus Dworski , Infineon Technologies, Villach, Austria
S. Sattler , Infineon Technologies Munich, Germany
pp. 963-971
Hideo Okawara , Agilent Technologies International Japan, Ltd. Tokyo, Japan
pp. 972-979
Guido Gronthoud , Philips Research Labs, Netherlands
Cristiano Cenci , Philips Research Labs, Netherlands
Martin Posch , Philips Semiconductors Gratkorn Austria
Thomas Burger , Philips Semiconductors Gratkorn Austria
Jose Pineda de Gyvez , Philips Research Labs, Netherlands
pp. 980-987
SESSION 35: EMBEDDED MEMORIES BIST AND REPAIR
Katsutoshi Uehara , Enterprise Server Division, Hitachi Ltd.
Minoru Itakura , Enterprise Server Division, Hitachi Ltd.
Masaji Kume , Enterprise Server Division, Hitachi Ltd.
Toru Kobayashi , Micro Device Division, Hitachi Ltd.
Masatoshi Hasegawa , Micro Device Division, Hitachi Ltd.
Hideki Hayashi , Hitachi ULSI Systems Co. Ltd.
pp. 988-996
Robert C. Aitken , Artisan Components, Caspian Court Sunnyvale, CA, USA
pp. 997-1005
Andrei Pavlov , University of Waterloo, Waterloo, ON, Canada
Jose Pineda de Gyvez , Philips Research Labs, Eindhoven, Netherlands
pp. 1006-1015
Toshimasa Namekawa , Toshiba Corporation, Kawasaki, Japan
Hiroshi Ito , Toshiba Corporation, Kawasaki, Japan
Osamu Wada , Toshiba Corporation, Kawasaki, Japan
Shuso Fujii , Toshiba Corporation, Kawasaki, Japan
pp. 1016-1023
SESSION 36: DELAY TESTING
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
pp. 1024-1033
Manan Syal , Virginia Tech, Blacksburg, VA.
Sreejit Chakravarty , Intel Architecture Group, Intel Corporation, Santa Clara, CA
pp. 1034-1043
Quming Zhou , Department of Electrical and Computer Engineering Rice University, Houston, TX
pp. 1044-1052
Puneet Gupta , Cadence Design Systems, TDA, Endicott, NY
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 1053-1060
SESSION 37: APPLICATION SERIES - BOARD AND SYSTEM-LEVEL DFT AND TEST
Charles A. Njinda , Procket Networks, Cadillac Court, Milpitas, CA
pp. 1061-1071
Sunil Kalidindi , IXIA Corporation., Calabasas CA,
Nghia Huynh , Cisco Systems Inc., San Jose CA,
Bill Eklow , Cisco Systems Inc., San Jose CA
Josh Goldstein , IXIA Corporation, Calabasas CA
pp. 1072-1077
Thomas J. Anderson , Wavecrest Corporatio, Technology Drive, San Jose, CA
pp. 1078-1080
SESSION 38: FORMALIZING AND SIMULATING ATE
Baolin Deng , University of Erlangen-Nuremberg, Germany
Wolfram Glauert , University of Erlangen-Nuremberg, Germany
pp. 1081-1090
M. Zambaldi , Infineon Technologies AG, Munich, Germany
pp. 1091-1099
R Raghuraman , Texas Instruments Ltd., Bangalore , India.
pp. 1100-1107
SESSION 39: TESTING FOR SPEED - NEW AND PRACTICAL METHODS
Bhaskar Chatterjee , University of Waterloo, Waterloo, ON, Canada
Ali Keshavarzi , Circuits Research, Intel Labs Hillsboro, OR, USA
pp. 1108-1117
Ramyanshu Datta , University of Texas at Austin Austin, TX
Ravi Gupta , University of Texas at Austin Austin, TX
Antony Sebastine , University of Texas at Austin Austin, TX
Jacob A. Abraham , University of Texas at Austin Austin, TX
Manuel d'Abreu , Sun Microsystems, Sunnyvale, CA
pp. 1118-1127
Kenneth A. Brand , Stanford University, Stanford, CA, USA
Erik Volkerink , Stanford University, Stanford, CA, USA
Edward J. McCluskey , Stanford University, Stanford, CA, USA
Subhasish Mitra , Intel Corporation, Folsom, CA, USA
pp. 1128-1137
SESSION 40: PICOSECOND JITTER TESTING
Dongwoo Hong , University of California, Santa Barbara
Chee-Kian Ong , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 1138-1147
Peter M. Levine , McGill University, Canada
Gordon W. Roberts , McGill University, Canada
pp. 1148-1157
Mike Li , Wavecrest, Technology Dr., San Jose, CA
Gerry Talbot , AMD, MA
Jan Wilstrup , Teradyne Inc., Fridley, MN
pp. 1158-1167
SESSION 41: APPLICATION SERIES - WAFER PROBE TECHNOLOGY
Frederick L. Taber , BiTS Workshop General Chair and IBM Microelectronics, LaGrangeville, NY
Philip W. Seitzer , Distinguished Member of Technical Staff, Agere Systems, Allentown PA
Jerry J. Broz , SWTW Technical Chair and International Test Solutions, Reno, NV
pp. 1168-1195
SESSION 42: WRAPPERS AND MORE
Qiang Xu , McMaster University, Hamilton, ON
pp. 1196-1202
Sandeep Kumar Goel , Philips Research, Netherlands
Erik Jan Marinissen , Philips Research, Netherlands
Anuja Sehgal , Duke University
pp. 1203-1212
Jing-Reng Huang , National Tsing Hua University, Taiwan
Chih-Wea Wang , National Tsing Hua University, Taiwan
Chih-Yen Lo , National Tsing Hua University, Taiwan
Li-Ming Denq , National Tsing Hua University, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Taiwan
Shin-Wei Hung , Global UniChip Corp., Taiwan
Jye-Yuan Lee , Global UniChip Corp., Taiwan
pp. 1213-1222
SESSION 43: DESIGN-FOR-AVAILABILITY
C. Metra , DEIS - U. of Bologna (Italy)
M. Omana , DEIS - U. of Bologna (Italy)
pp. 1223-1231
Zeljko Zilic , McGill University, Canada
Man Wah Chiang , McGill University, Canada
Katarzyna Radecka , Concordia University, Canada
pp. 1232-1241
Kaijie Wu , Polytechnic University, Brooklyn, NY
Grigori Kuznetsov , University of Potsdam, Germany
Michael Goessel , University of Potsdam, Germany
pp. 1242-1248
SESSION 44: ADVANCES IN TESTER ARCHITECTURE
Burnell G. West , Credence, Baytech Drive, San Jose, CA
Michael F. Jones , Credence, Baytech Drive, San Jose, CA
pp. 1249-1254
Michael Jones , Credence Systems Corporation, San Jose, CA
Russell Poffenberger , Credence Systems Corporation, San Jose, CA
Maurizio Gavardoni , Credence Systems Corporation, San Jose, CA
pp. 1263-1268
SESSION 45: ADVANCES IN DELAY TESTING
Bipul C Paul , Purdue University
Kaushik Roy , Purdue University
pp. 1269-1275
M. Rosales , Univ. de les Illes Balears, Palma de Mallorca, Spain
J.L. Rosello , Univ. de les Illes Balears, Palma de Mallorca, Spain
J. Segura , Univ. de les Illes Balears, Palma de Mallorca, Spain
A. Keshavarzi , Circuit Research Labs., Intel Corporation, Portland, OR, USA
pp. 1276-1284
Cam Lu , LSI Logic Corporation, Fort Collins, CO
John Van Slyke , LSI Logic Corporation, Fort Collins, CO
Prabhu Krishnamurthy , LSI Logic Corporation, Fort Collins, CO
Robert Madge , LSI Logic Corporation, Fort Collins, CO
Martin Keim , Mentor Graphics Corporation
Mark Kassab , Mentor Graphics Corporation
Janusz Rajski , Mentor Graphics Corporation
pp. 1285-1294
SESSION 46: APPLICATION SERIES - JITTER IN TEST
Andy Kuo , University of British Columbia
Touraj Farahmand , University of British Columbia
Nelson Ou , University of British Columbia
Andre Ivanov , University of British Columbia
Sassan Tabatabaei , Guide Technology, Sunnyvale, CA
pp. 1295-1302
Gert Hansel , Infineon Technologies AG, Munich, Germany
pp. 1303-1312
Sassan Tabatabaei , Guide Technology, Sunnyvale, CA
Freddy Ben-Zeev , Guide Technology, Sunnyvale, CA
pp. 1313-1321
SESSION 47: ON-LINE TESTING AND FAULT TOLERANCE AT LOW COST
Nur A. Touba , Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
Shalini Ghosh , Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
pp. 1322-1331
F. Corno , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
M. Sonza Reorda , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
S. Tosato , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
F. Esposito , FIAT Auto - Product and Process Engineering - Integrated Chassis Control - Torino, Italy
pp. 1332-1339
Haibo Wang , Southern Illinois University Carbondale
Spyros Tragoudas , Southern Illinois University Carbondale
pp. 1340-1348
SESSION 48: ADVANCES IN SOC TEST
Erik Larsson , Linkopings Universitet, Sweden
pp. 1349-1358
Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 1359-1368
Hamid Sharif , University of Nebraska
Chunsheng Liu , University of Nebraska
D.K. Pradhan , University of Bristol, UK
pp. 1369-1378
SESSION 49: ADC TESTING
Beatriz Olleta , Iowa State University Ames, IA
Degang Chen , Iowa State University Ames, IA
Randall L. Geiger , Iowa State University Ames, IA
pp. 1379-1388
Hongjoong Shin , University of Texas at Austin, Austin, TX
Ji Hwan (Paul) Chun , University of Texas at Austin, Austin, TX
Hak-soo Yu , University of Texas at Austin, Austin, TX
pp. 1389-1397
PANEL 1: OPEN ARCHITECTURE ATE: REALITY OR DREAM?
Sergio M Perez , Advantest America, Inc.
pp. 1409
Dr. Burnell G. West , Credence Systems Corporation, San Jose, USA
pp. 1410
PANEL 2: SECURITY VS. TEST QUALITY: CAN WE ONLY HAVE ONE AT A TIME?
Herve FLEURY , Philips Semiconductors, France
pp. 1412
PANEL 3: GLAMOROUS ANALOG TESTABILITY - WE ALREADY TEST THEM AND SHIP THEM... SO WHAT IS THE PROBLEM?
PANEL 4: 100 DPM IN NANOMETER TECHNOLOGY - IS IT ACHIEVABLE?
Greg Aldrich , Mentor Graphics Corporation
pp. 1417
Brady R. Benware , LSI Logic Corporation, Fort Collins, CO
pp. 1418
Sanjay Sengupta , Intel Corp. Santa Clara, CA, USA
pp. 1421
Tom Storey , BAE Systems Manassas, VA
pp. 1422
PANEL 5: WHAT DO YOU MEAN MY BOARD TEST STINKS?
Bill Eklow , Cisco Systems, Inc.
pp. 1423
Jay J. Nejedlo , Intel Corporation at Hillsboro, OR
pp. 1424
Rob Jukna , Jabil Circuit Inc.- Advanced Manufacturing Technology
pp. 1425
Kenneth P. Parker , Agilent Technologies Loveland, CO
pp. 1426
Michael J Smith , Teradyne Inc, North Reading, MA. USA
pp. 1427
PANEL 6: DUDE! WHERE?S MY DATA? - CRACKING OPEN THE HERMETICALLY SEALED TESTER
Phil Nigh , IBM Technology and Systems Group Essex Junction, VT
pp. 1429
PANEL 7: COST OF TEST: TAKING CONTROL
Nilanjan Mukherjee , Mentor Graphics Corporation, Wilsonville, OR
pp. 1431
PANEL 8: IS "DESIGN-TO-PRODUCTION" THE ULTIMATE ANSWER FOR JITTER, NOISE, AND BER CHALLENGES FOR MULTI-GB/S ICS?
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
pp. 1434
John C. Johnson , Intel Corporation, Test Platform Architecture and Development
pp. 1435
Jim Sproch , Synopsys Test Automation Products Group
pp. 1437
PANEL 9: DIAGNOSIS MEETS PHYSICAL FAILURE ANALYSIS: HOW LONG CAN WE SUCCEED?
Thomas W. Bartenstein , Cadence Design Inc., Endicott, NY
pp. 1439
Edward I. Jr. Cole , Sandia National Laboratories Albuquerque, USA
pp. 1440
PANEL 10: INVESTMENT VS. YIELD RELATIONSHIP FOR MEMORIES IN SOC
Jitendra B. Khare , Ample Communications, Inc., Fremont, CA USA.
pp. 1445
Joseph A. Reynick , eSilicon Corporation, Allentown, Pennsylvania, USA
pp. 1446
Jun Qian , Cisco Systems, Inc. San Jose, USA
pp. 1447
ITC 2003 BEST PAPER:
T.M. Mak , Intel Corporation
Anne Meixner , Intel Corporation
pp. 1448-1456
Author Index
pp. 1457
7 ms
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