- I
- ITC
- 2004
- International Test Conference 2004 (ITC'04)
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International Test Conference 2004 (ITC'04) Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0 Table of Contents
 | Cover |
 | Introduction |
 | SESSION 1: PLENARY |
 | SESSION 2: MICROPROCESSOR TEST |
Mo Bashir, Intel Corporation. Hillsboro, OR, USA
Kathy Tian, Intel Corporation. Santa Clara, CA, USA pp. 23-30
J. Zeng, Freescale Semiconductor Inc., Austin, TX
M. Abadir, Freescale Semiconductor Inc., Austin, TX
L. Wang, University of California, Santa Barbara, CA
J. Abraham, University of Texas at Austin, Austin, TX pp. 31-37
 | SESSION 3: LOGIC BIST |
Liyang Lai, University of Illinois at Urbana-Champaign pp. 57-66
 | SESSION 4: BIST FOR JITTER |
Mani Soma, University of Washington, Seattle, WA pp. 77-84
Henry Lin, University of Washington, Seattle, WA
Mani Soma, University of Washington, Seattle, WA
Hosam Haggag, Santa Clara Design Center, National Semiconductor, Santa Clara, CA
Jeff Huard, Tacoma Design Center, National Semiconductor, Federal Way, WA
Jim Braatz, Tacoma Design Center, National Semiconductor, Federal Way, WA pp. 85-94
 | SESSION 5: MEMORY TESTING |
Ming-Jer Kao, Industrial Technology Research Institute Hsinchu, Taiwan
Yeong-Jar Chang, SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan
Wen-Ching Wu, SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan pp. 124-133
 | SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS |
Peilin Song, IBM T.J. Watson Research Center, Yorktown Heights, NY
Alan J. Weger, IBM T.J. Watson Research Center, Yorktown Heights, NY
Tian Xia, University of Vermont, Burlington, VT pp. 140-147
 | SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE |
Sang H. Baeg, Cisco Systems, Inc., Tasman Drive San Jose, CA pp. 173-180
 | SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST |
Jason Saw, Invantest Corporation, San Jose, CA, USA pp. 181-189
Brian Swing, Semiconductor Test, Teradyne Inc., Boston, MA
John Pane, Semiconductor Test, Teradyne Inc., Boston, MA pp. 190-196
 | SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS |
Wangqi Qiu, Texas A&M University, College Station, TX
Jing Wang, Texas A&M University, College Station, TX
Zhuo Li, Dept. of Electrical Engineering, Texas A&M University, College Station, TX
Weiping Shi, Dept. of Electrical Engineering, Texas A&M University, College Station, TX pp. 223-231
 | SESSION 10: MIXED-SIGNAL BIST AND DFT |
Geert Seuren, Philips Research Electronics Design, Netherlands
Tom Waayers, Philips Research Electronics Design, Netherlands pp. 281-289
 | SESSION 11: ADVANCES IN TESTING FOR DEFECTS |
R. Daasch, LSI Logic Corporation, Gresham, OR pp. 300-308
 | SESSION 12: ADVANCES IN DFT |
Bo Yang, Polytechnic University, Brooklyn, NY
Kaijie Wu, Polytechnic University, Brooklyn, NY pp. 339-344
 | SESSION 13: BOARD AND SYSTEM TEST: BOARD TEST EFFECTIVENESS |
A. Kumar, Indian Institute of Technology, Delhi, India pp. 375-383
 | SESSION 14: DEVELOPMENTS IN ATE SOFTWARE STANDARDS |
Mark Elston, Advantest America R&D Center Inc., Santa Clara, CA
Bruce Parnas, Advantest America R&D Center Inc., Santa Clara, CA pp. 413-422
Don Organ, Inovys Corporation Pleasanton, CA. USA pp. 423-431
 | SESSION 15: HANDLING OF UNKNOWNS |
 | SESSION 16: EMERGING TECHNOLOGIES FAULT MODELING and TOLERANCE |
 | SESSION 17: ADVANCES IN DIAGNOSIS |
Chen Wang, Mentor Graphics Corporation, Wilsonville, OR pp. 498-507
T. Vogels, Carnegie Mellon University, Pittsburgh, PA
T. Zanon, Carnegie Mellon University, Pittsburgh, PA
R. Desineni, Carnegie Mellon University, Pittsburgh, PA
W. Maly, Carnegie Mellon University, Pittsburgh, PA
J. G. Brown, Carnegie Mellon University, Pittsburgh, PA
Y. Fei, Carnegie Mellon University, Pittsburgh, PA
X. Huang, Carnegie Mellon University, Pittsburgh, PA
M. Mishra, Carnegie Mellon University, Pittsburgh, PA
V. Rovner, Carnegie Mellon University, Pittsburgh, PA
S. Tiwary, Carnegie Mellon University, Pittsburgh, PA pp. 508-517
 | SESSION 18: TEST ECONOMICS |
Xinli Gu, Cisco Systems, Inc., San Jose, CA
Abby Lee, Cisco Systems, Inc., San Jose, CA
Mark Kassab, Mentor Graphics Corporation, Wilsonville, OR pp. 525-533
 | SESSION 19: BOARD AND SYSTEM TEST: EXTENDING BOUNDARY-SCAN TO RF AND HS SERIAL TESTING |
Juha Hakkinen, Electrical and Information Engineering, Electronics Laboratory, University of Oulu, Finland
Pekka Syri, Electrical and Information Engineering, Electronics Laboratory, University of Oulu, Finland
Markku Moilanen, Optoelectronics and Measurement Techniques Laboratory, University of Oulu, Finland pp. 551-559
Jeff Rearick, Agilent Technologies ASIC Product Division Fort Collins, CO
Krista Dorner, Agilent Technologies ASIC Product Division Fort Collins, CO pp. 560-566
 | SESSION 20: SQUEEZING THE PICOSECONDS |
A.T. Sivaram, Credence Inc Intel, Baytech Drive, San Jose, CA pp. 587-596
 | SESSION 21: ATPG/FAULT SIMULATION SPECIALTIES |
 | SESSION 22: INTERCONNECT TESTING AND FAULT DIAGNOSIS IN FPGAS |
 | SESSION 23: INDUSTRY CASE STUDIES IN TESTING |
A. Cabbibo, LSI Logic Corporation, Gresham, Oregon
J. Conder, LSI Logic Corporation, Gresham, Oregon
M. Jacobs, LSI Logic Corporation, Gresham, Oregon pp. 655-660
 | SESSION 24: LECTURE SERIES - TEST TRENDS AND CHALLENGES |
T. M. Mak, Design Technology, Intel Corporation pp. 679-687
 | SESSION 25: BOARD AND SYSTEM TEST: SYSTEM AND FIELD TEST |
Toai Vo, Cisco Systems Inc., San Jose CA pp. 704-710
Yujun Zhang, Chinese Academy of Sciences. Beijing, China pp. 719-727
 | SESSION 26: ATE FOR THE FASTEST DEVICES |
 | SESSION 27: SOC: MIXED SIGNALS, SIZE AND SPEED |
K. Nikila, Texas Instruments Pvt. Ltd., Bangalore, India pp. 773-782
 | SESSION 28: RF TESTING |
Dana Brown, IBM Corporation Essex Junction, VT, USA
Randy Wolf, IBM Corporation Essex Junction, VT, USA
Jing Li, IBM Corporation Essex Junction, VT, USA pp. 793-800
 | ESSION 29: STATE SPACE EXPLORATION AND TEST GENERATION |
 | SESSION 30: SOC TEST CASE STUDIES |
 | SESSION 31: BOARD AND SYSTEM TEST: BOARD AND SYSTEM-LEVEL BIST TECHNIQUES |
CJ Clark, Intellitech Corporation, Durham, NH pp. 857-866
Liviu Miclea, Department of Automation , Technical University of Cluj-Napoca, Romania
Szilard Enyedi, Department of Automation , Technical University of Cluj-Napoca, Romania
Gavril Toderean, Department of Telecommunications,Technical University of Cluj-Napoca, Romania pp. 867-874
 | SESSION 32: TEST OF DIGITAL, ANALOG AND MEMS C |
Fei Su, Duke University, Durham, NC pp. 883-892
T. Balen, DELET-UFRGS, Univ. Fed. do Rio Grande do Sul Porto Alegre, Brazil
A. Jr. Andrade, DELET-UFRGS, Univ. Fed. do Rio Grande do Sul Porto Alegre, Brazil
F. Azais, Universite de Montpellier II Montpellier Cedex 5, France
M. Renovell, Universite de Montpellier II Montpellier Cedex 5, France
M. Lubaszewski, IMSE-CNM Inst. de Microelectr. De Sevilla Sevilla, Spain pp. 893-902
Ali Muhtaroglu, Intel Corporation, Logic Technology Development, Hillsboro, OR
Benoit Provost, Intel Corporation, Logic Technology Development, Hillsboro, OR
Greg Taylor, Intel Corporation, Logic Technology Development, Hillsboro, OR pp. 903-906
 | SESSION 33: TEST COMPRESSION |
 | SESSION 34: MIXED-SIGNAL TEST TECHNIQUES |
H. Mattes, Infineon Technologies Munich, Germany pp. 963-971
Hideo Okawara, Agilent Technologies International Japan, Ltd. Tokyo, Japan pp. 972-979
 | SESSION 35: EMBEDDED MEMORIES BIST AND REPAIR |
 | SESSION 36: DELAY TESTING |
Quming Zhou, Department of Electrical and Computer Engineering Rice University, Houston, TX
Kartik Mohanram, Department of Electrical and Computer Engineering Rice University, Houston, TX pp. 1044-1052
 | SESSION 37: APPLICATION SERIES - BOARD AND SYSTEM-LEVEL DFT AND TEST |
 | SESSION 38: FORMALIZING AND SIMULATING ATE |
W. Ecker, Infineon Technologies AG, Munich, Germany pp. 1091-1099
 | SESSION 39: TESTING FOR SPEED - NEW AND PRACTICAL METHODS |
Ravi Gupta, University of Texas at Austin Austin, TX pp. 1118-1127
 | SESSION 40: PICOSECOND JITTER TESTING |
Mike Li, Wavecrest, Technology Dr., San Jose, CA pp. 1158-1167
 | SESSION 41: APPLICATION SERIES - WAFER PROBE TECHNOLOGY |
William R. Mann, SWTW General Chair and Rockwell International, Newport Beach, CA
Frederick L. Taber, BiTS Workshop General Chair and IBM Microelectronics, LaGrangeville, NY
Philip W. Seitzer, Distinguished Member of Technical Staff, Agere Systems, Allentown PA
Jerry J. Broz, SWTW Technical Chair and International Test Solutions, Reno, NV pp. 1168-1195
 | SESSION 42: WRAPPERS AND MORE |
Qiang Xu, McMaster University, Hamilton, ON pp. 1196-1202
 | SESSION 43: DESIGN-FOR-AVAILABILITY |
TM Mak, Intel Corp., Santa Clara (CA) pp. 1223-1231
Kaijie Wu, Polytechnic University, Brooklyn, NY pp. 1242-1248
 | SESSION 44: ADVANCES IN TESTER ARCHITECTURE |
 | SESSION 45: ADVANCES IN DELAY TESTING |
S.A. Bota, Univ. de les Illes Balears, Palma de Mallorca, Spain
M. Rosales, Univ. de les Illes Balears, Palma de Mallorca, Spain
J.L. Rosello, Univ. de les Illes Balears, Palma de Mallorca, Spain
J. Segura, Univ. de les Illes Balears, Palma de Mallorca, Spain
A. Keshavarzi, Circuit Research Labs., Intel Corporation, Portland, OR, USA pp. 1276-1284
Cam Lu, LSI Logic Corporation, Fort Collins, CO pp. 1285-1294
 | SESSION 46: APPLICATION SERIES - JITTER IN TEST |
Andy Kuo, University of British Columbia pp. 1295-1302
 | SESSION 47: ON-LINE TESTING AND FAULT TOLERANCE AT LOW COST |
Shalini Ghosh, Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
Nur A. Touba, Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
Sugato Basu, Dept. of Computer Sciences, University of Texas, Austin, TX pp. 1322-1331
F. Corno, Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
M. Sonza Reorda, Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
S. Tosato, Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
F. Esposito, FIAT Auto - Product and Process Engineering - Integrated Chassis Control - Torino, Italy pp. 1332-1339
Haibo Wang, Southern Illinois University Carbondale pp. 1340-1348
 | SESSION 48: ADVANCES IN SOC TEST |
Erika Cota, Universidade Federal do Rio Grande do Sul, Brazil pp. 1369-1378
 | SESSION 49: ADC TESTING |
Hak-soo Yu, University of Texas at Austin, Austin, TX pp. 1389-1397
 | PANEL 1: OPEN ARCHITECTURE ATE: REALITY OR DREAM? |
 | PANEL 2: SECURITY VS. TEST QUALITY: CAN WE ONLY HAVE ONE AT A TIME? |
 | PANEL 3: GLAMOROUS ANALOG TESTABILITY - WE ALREADY TEST THEM AND SHIP THEM... SO WHAT IS THE PROBLEM? |
 | PANEL 4: 100 DPM IN NANOMETER TECHNOLOGY - IS IT ACHIEVABLE? |
Phil Nigh, IBM Technology and Systems Group, Essex Junction, VT pp. 1420
 | PANEL 5: WHAT DO YOU MEAN MY BOARD TEST STINKS? |
Rob Jukna, Jabil Circuit Inc.- Advanced Manufacturing Technology pp. 1425
 | PANEL 6: DUDE! WHERE?S MY DATA? - CRACKING OPEN THE HERMETICALLY SEALED TESTER |
Phil Nigh, IBM Technology and Systems Group Essex Junction, VT pp. 1429
 | PANEL 7: COST OF TEST: TAKING CONTROL |
 | PANEL 8: IS "DESIGN-TO-PRODUCTION" THE ULTIMATE ANSWER FOR JITTER, NOISE, AND BER CHALLENGES FOR MULTI-GB/S ICS? |
John C. Johnson, Intel Corporation, Test Platform Architecture and Development pp. 1435
Jim Sproch, Synopsys Test Automation Products Group pp. 1437
 | PANEL 9: DIAGNOSIS MEETS PHYSICAL FAILURE ANALYSIS: HOW LONG CAN WE SUCCEED? |
 | PANEL 10: INVESTMENT VS. YIELD RELATIONSHIP FOR MEMORIES IN SOC |
Jun Qian, Cisco Systems, Inc. San Jose, USA pp. 1447
 | ITC 2003 BEST PAPER: |
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