This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
International Test Conference 2004 (ITC'04)
SPEED CLUSTERING OF INTEGRATED CIRCUITS
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
Kenneth A. Brand, Stanford University, Stanford, CA, USA
Erik Volkerink, Stanford University, Stanford, CA, USA
Edward J. McCluskey, Stanford University, Stanford, CA, USA
Subhasish Mitra, Intel Corporation, Folsom, CA, USA
Experimental data on 0.18 test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.
Citation:
Kenneth A. Brand, Erik Volkerink, Edward J. McCluskey, Subhasish Mitra, "SPEED CLUSTERING OF INTEGRATED CIRCUITS," itc, pp.1128-1137, International Test Conference 2004 (ITC'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.