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International Test Conference 2003 (ITC'03)
Charlotte, NC, USA
September 30-October 02
ISBN: 0-7803-8107-6
Table of Contents
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Session 1: Plenary
Session 2: Memory Testing And Diagnosis
J. M. Portal, IMT - Technop?le de Ch?teau Gombert
H. Aziza, IMT - Technop?le de Ch?teau Gombert; ST-Microelectronics
D. N?, ST-Microelectronics
pp. 23
Chih-Wea Wang, National Tsing Hua University
Kuo-Liang Cheng, National Tsing Hua University
Jih-Nung Lee, National Tsing Hua University
Yung-Fa Chou, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Frank Huang, Spirox Co.
Hong-Tzer Yang, Spirox Co.
pp. 29
Session 3: Jitter Testing Techniques for > GB/S TX/RX Links
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma, University of Washington, Seattle, WA
Masahiro Ishida, Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Makoto Kurosawa, Advantest Corporation, Gunma, Japan
Hirobumi Musha, Advantest Corporation, Gunma, Japan
pp. 58
Henry C. Lin, University of Washington, Seattle, WA
Karen Taylor, University of Washington, Seattle, WA
Alan Chong, University of Washington, Seattle, WA
Eddie Chan, University of Washington, Seattle, WA
Mani Soma, University of Washington, Seattle, WA
Hosam Haggag, Santa Clara Design Center, National Semiconductor, Santa Clara, CA
Jeff Huard, Tacoma Design Center, National Semiconductor, Federal Way, WA
Jim Braatz, Tacoma Design Center, National Semiconductor, Federal Way, WA
pp. 67
Session 4: High Yield And Effective Testing And Burn-In
Yoshihito Nishizaki, Kawasaki Microelectronics, Inc.
Osamu Nakayama, Kawasaki Microelectronics, Inc.
Chiaki Matsumoto, Kawasaki Microelectronics, Inc.
Yoshitaka Kimura, Kawasaki Microelectronics, Inc.
Toshimi Kobayashi, Kawasaki Microelectronics, Inc.
Hiroyuki Nakamura, Kawasaki Microelectronics, Inc.
pp. 85
Oleg Semenov, University of Waterloo, Canada
Arman Vassighi, University of Waterloo, Canada
Manoj Sachdev, University of Waterloo, Canada
Ali Keshavarzi, Intel Corporation, Hillsboro, OR
C.F. Hawkins, University of New Mexico, Albuquerque
pp. 95
Session 5: Crosstalk And Delay Test
Xiaoliang Bai, University of California, San Diego, CA
Sujit Dey, University of California, San Diego, CA
Angela Krstic, University of California, Santa Barbara, CA
pp. 112
Rahul Kundu, Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
pp. 122
Session 6: Improving Design Validation Coverage
S. R. Seward, University of Arkansas, Fayetteville
P. K. Lala, University of Arkansas, Fayetteville
pp. 131
Amir Hekmatpour, IBM Microelectronics, Research Triangle Park, North Carolina
James Coulter, IBM Microelectronics, Research Triangle Park, North Carolina
pp. 148
Session 7: Lecture Series-Board And System Test: Is PXI The Future of Functional Board Test?
Eric Starkloff, National Instruments, Austin, TX
Tim Fountain, National Instruments, Austin, TX
Garth Black, National Instruments, Austin, TX
pp. 156
Session 8: Pushing The Envelope of ATE
Session 9: ADC Test
S. Bernard, University of Montpellier / CNRS, France
M. Comte, University of Montpellier / CNRS, France
F. Aza?, University of Montpellier / CNRS, France
Y. Bertrand, University of Montpellier / CNRS, France
M. Renovell, University of Montpellier / CNRS, France
pp. 201
Gwenol? Maugard, Raheen Industrial Estate, Limerick, Ireland
Carsten Wegener, University College Cork, Ireland
Tom O'Dwyer, Raheen Industrial Estate, Limerick, Ireland
Michael Peter Kennedy, University College Cork, Ireland
pp. 210
Le Jin, Texas Instruments Inc., Dallas
Kumar Parthasarathy, Iowa State University, Ames
Turker Kuyel, Iowa State University, Ames
Degang Chen, Texas Instruments Inc., Dallas
Randall L. Geiger, Texas Instruments Inc., Dallas
pp. 218
Session 10: Advances in Testing And Analysis Methods
Franco Stellari, IBM T.J. Watson Research Center, Yorktown Heights, NY
Peilin Song, IBM T.J. Watson Research Center, Yorktown Heights, NY
Moyra K. McManus, IBM T.J. Watson Research Center, Yorktown Heights, NY
Robert Gauthier, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Alan J. Weger, IBM T.J. Watson Research Center, Yorktown Heights, NY
Kiran Chatty, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Mujahid Muhammad, IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Pia Sanda, IBM Systems Group, Poughkeepsie, NY
pp. 236
Romain Desplats, CNES- French Space Agency, France
Felix Beaudoin, CNES- French Space Agency, France
Philippe Perdu, CNES- French Space Agency, France
Nagamani Nataraj, NPTest, San Jose, CA
Ted Lundquist, NPTest, San Jose, CA
Ketan Shah, NPTest, San Jose, CA
pp. 254
Session 11: Novel ATPG Approaches
Vishwani D. Agrawal, Rutgers University, Piscataway, NJ
A. V. S. S. Prasad, Agere Systems, Bangalore, India
Madhusudan V. Atre, Agere Systems, Bangalore, India
pp. 274
Liang Zhang, Virginia Tech, Blacksburg, VA
Indradeep Ghosh, Fujitsu Labs. of America Inc., Sunnyvale, CA
Michael Hsiao, Virginia Tech, Blacksburg, VA
pp. 290
Session 12: Advances in Diagnostics
Thomas J. Vogels, Carnegie Mellon University, Pittsburgh, PA
Wojciech Maly, Carnegie Mellon University, Pittsburgh, PA
R.D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
pp. 309
Yu Huang, Mentor Graphics Corporation, Wilsonville, OR
Wu-Tung Cheng, Mentor Graphics Corporation, Wilsonville, OR
Sudhakar M. Reddy, University of Iowa, Iowa City
Cheng-Ju Hsieh, Faraday Technology Corporation
Yu-Ting Hung, Faraday Technology Corporation
pp. 319
Zhiyuan Wang, University of California, Santa Barbara
Kun-Han Tsai, Mentor Graphics Corporation
Malgorzata Marek-Sadowska, University of California, Santa Barbara
Janusz Rajski, Mentor Graphics Corporation
pp. 329
Session 13: Board And System Test: Advanced Applications of Boundary-Scan
YongJoon Kim, Yonsei University
DongSub Song, Yonsei University
YongSeung Shin, Yonsei University
Sunghoon Chun, Yonsei University
Sungho Kang, Yonsei University
pp. 349
Kevin Melocco, Cadence Design Systems - Test Design Automation - Endicott, NY
Hina Arora, Cadence Design Systems - Test Design Automation - Endicott, NY
Paul Setlak, Cadence Design Systems - Test Design Automation - Endicott, NY
Gary Kunselman, IBM Microelectronics - DFTS Development and Methodology - Burlington, VT
Shazia Mardhani, Sun Microsystems - High End Server Engineering - Burlington, MA
pp. 358
Henk D.L. Hollmann, Philips Research Laboratories
Erik Jan Marinissen, Philips Research Laboratories
Bart Vermeulen, Philips Research Laboratories
pp. 369
Session 14: Embedded Memory BIST and Repair
D. Appello, ST Microelectronics, Cornaredo, Italy
P. Bernardi, Politecnico di Torino, Italy
A. Fudoli, ST Microelectronics, Cornaredo, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
V. Tancorre, ST Microelectronics, Cornaredo, Italy
M. Violante, Politecnico di Torino, Italy
pp. 379
Theo J. Powell, Texas Instruments Inc.
Wu-Tung Cheng, Mentor Graphics Corporation
Joseph Rayhawk, Mentor Graphics Corporation
Omer Samman, Mentor Graphics Corporation
Paul Policke, Texas Instruments Inc.
Sherry Lai, Texas Instruments Inc.
pp. 386
Jin-Fu Li, National Central University
Jen-Chieh Yeh, National Tsing Hua University
Rei-Fu Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Peir-Yuan Tsai, ADMTek Incorporated
Archer Hsu, ADMTek Incorporated
Eugene Chow, ADMTek Incorporated
pp. 393
Session 15: Interface Magic
Session 16: Test And Verification For Cores And SOCS
Tomokazu Yoneda, Nara Institute of Science and Technology, Japan
Tetsuo Uchiyama, SOC Design Center, CANON INC.
Hideo Fujiwara, Nara Institute of Science and Technology, Japan
pp. 415
Yu-Shen Yang, University of Toronto, ON
J. Brandon Liu, University of Toronto, ON
Paul Thadikaran, Intel Corporation, OR
Andreas Veneris, University of Toronto, ON
pp. 423
N. Kranitis, University of Athens, Greece
G. Xenoulis, University of Piraeus, Greece
A. Paschalis, University of Athens, Greece
D. Gizopoulos, University of Piraeus, Greece
Y. Zorian, Virage Logic, Fremont, CA
pp. 431
Session 17: Keep Compressing This Test Data!
Armin W?rtenberger, University of Innsbruck, Austria
Christofer S. Tautermann, University of Innsbruck, Austria
Sybille Hellebrand, University of Innsbruck, Austria
pp. 451
Session 18: Low-Power Scan
Bhargab B. Bhattacharya, Indian Statistical Institute
Sharad C. Seth, University of Nebraska-Lincoln
Sheng Zhang, University of Nebraska-Lincoln
pp. 470
Takaki Yoshida, Matsushita Electric Industrial Co., Ltd.
Masafumi Watati, Matsushita Electric Industrial Co., Ltd.
pp. 480
Y. Bonhomme, LIRMM, Universit? Montpellier II/CNRS, France
P. Girard, LIRMM, Universit? Montpellier II/CNRS, France
L. Guiller, Synopsys Inc., Mountain View, CA
C. Landrault, LIRMM, Universit? Montpellier II/CNRS, France
S. Pravossoudovitch, LIRMM, Universit? Montpellier II/CNRS, France
pp. 488
Session 19: Lecture Series-Board And System Test: IEEE 1149.6-A Practical Perspective
Bill Eklow, Cisco Systems Inc., San Jose CA
Carl Barnhart, Cadence Design Systems, Ojai, CA
Mike Ricchetti, Intellitech, Durham, NH
Terry Borroz, Teradyne, North Reading, MA
pp. 494
Session 20: Extremely Low-Cost Testers
Session 21: Application Series-Developing Test Interfaces
Jie Sun, Wavecrest Corporation, San Jose, CA
Mike Li, Wavecrest Corporation, San Jose, CA
pp. 528
Session 22: Practical Application of IDDQ
Xiaoyun Sun, University of Minnesota, Minneapolis
Larry Kinney, University of Minnesota, Minneapolis
Bapiraju Vinnakota, University of Minnesota, Minneapolis
pp. 545
Yukio Okuda, Platform Technology Center, Sony Corp.
Nobuyuki Furukawa, Sony Semicon Kyushu Corp.
pp. 555
C. Schuermyer, LSI Logic Corporation, Gresham, Oregon
B. Benware, LSI Logic Corporation, Gresham, Oregon
K. Cota, LSI Logic Corporation, Gresham, Oregon
R. Madge, LSI Logic Corporation, Gresham, Oregon
R. Daasch, Portland State University, Oregon
L. Ning, Portland State University, Oregon
pp. 565
Session 23: Delay Test
Puneet Gupta, Virginia Tech, Blacksburg
Michael S. Hsiao, Virginia Tech, Blacksburg
pp. 584
Session 24: Optimizing Efficiency in SOC Testing
?rika Cota, Universidade Federal do Rio Grande do Sul
Luigi Carro, Universidade Federal do Rio Grande do Sul
Fl?vio Wagner, Universidade Federal do Rio Grande do Sul
Marcelo Lubaszewski, Universidade Federal do Rio Grande do Sul
pp. 612
Session 25: Board And System Test: AC-Interconnect Board Test Techniques
Suzette Vandivier, Agilent Technologies, Ft. Collins, CO.
Mark Wahl, Agilent Technologies, Ft. Collins, CO.
Jeff Rearick, Agilent Technologies, Ft. Collins, CO.
pp. 632
Ivan Duzevik, National Semiconductor, South Portland, Maine
pp. 640
Session 26: RF Testing
Jos? Pineda de Gyvez, Philips Research Laboratories
Guido Gronthoud, Philips Research Laboratories
Rashid Amine, Philips Research Laboratories
pp. 651
Achintya Halder, Georgia Institute of Technology, Atlanta
Soumendu Bhattacharya, Georgia Institute of Technology, Atlanta
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
pp. 665
Session 27: Lecture Series-Introduction to MEMS
Tamal Mukherjee, Carnegie Mellon University, Pittsburgh, PA
pp. 681
MEMS Fabrication (Abstract)
Gary K. Fedder, Carnegie Mellon University, Pittsburgh, PA
pp. 691
Session 28: Application of IDDX
Wanli Jiang, Guidant Corporation
Eric Peterson, Guidant Corporation
Bob Robotka, Guidant Corporation
pp. 699
Dhruva Acharyya, University of Maryland, Baltimore County
Jim Plusquellic, University of Maryland, Baltimore County
pp. 709
B. Alorda, Intel Corporation, Hillsboro, Oregon
B. Bloechel, Intel Corporation, Hillsboro, Oregon
A. Keshavarzi, Intel Corporation, Hillsboro, Oregon
J. Segura, Univ. de les Illes Balears, Dept. F?sica, Palma de Mallorca, Spain
pp. 719
Session 29: Logic BIST
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
Chen Wang, Mentor Graphics Corporation
Sudhakar M. Reddy, University of Iowa
pp. 745
Session 30: Microprocessor Test
Session 31: Board And System Test: Advances in Testing Microprocessor Motherboards
Leon van de Logt, Philips Research Eindhoven, The Netherlands
Frank van der Heyden, Philips Research Eindhoven, The Netherlands
Tom Waayers, Philips Research Eindhoven, The Netherlands
pp. 785
Session 32: Latest Developments in ATE Software
A. Benso, Politecnico di Torino, Italy
S. Di Carlo, Politecnico di Torino, Italy
G. Di Natale, Politecnico di Torino, Italy
P. Prinetto, Politecnico di Torino, Italy
L. Tagliaferri, Politecnico di Torino, Italy
pp. 802
Paul Buxton, The Alba Centre, The Alba Campus, Livingston, Scotland
Paul Tabor, Test Advantage Inc, Tempe, AZ
pp. 818
Session 33: Lecture Series-MEMS Testing
Jeremy A. Walraven, Sandia National Laboratories, Albuquerque, NM
pp. 828
Theresa Maudie, Motorola, Tempe, AZ
Alex Hardt, Motorola, Tempe, AZ
Rick Nielsen, Motorola, Tempe, AZ
Dennis Stanerson, Motorola, Tempe, AZ
Ron Bieschke, Motorola, Tempe, AZ
Mike Miller, Motorola, Tempe, AZ
pp. 843
Session 34: Failure Mechanisms And Test Solutions For DSM ICS
W. Maly, Carnegie Mellon University, Pittsburgh, PA
T. Zanon, Carnegie Mellon University, Pittsburgh, PA
T. Vogels, Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton, Carnegie Mellon University, Pittsburgh, PA
T. Storey, PDF Solutions
pp. 856
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
Kumar N. Dwarakanath, Carnegie Mellon University, Pittsburgh, PA
Anirudh B. Shah, Carnegie Mellon University, Pittsburgh, PA
pp. 876
Martin Oma?, D.E.I.S. University of Bologna, Italy
Daniele Rossi, D.E.I.S. University of Bologna, Italy
Cecilia Metra, D.E.I.S. University of Bologna, Italy
pp. 886
Session 35: Can Concurrent Detection Be Achieved At Low Cost?
B. Kiran Kumar, University of Arkansas, Fayetteville
P. K. Lala, University of Arkansas, Fayetteville
pp. 912
Session 36: Test Economics
H. Hashempour, Northeastern University, Boston, Mass
F. J. Meyer, Northeastern University, Boston, Mass
F. Lombardi, Northeastern University, Boston, Mass
F. Karimi, LTX Corp., San Jose, CA
pp. 927
Session 37: Board And System Test: Testing Multiboard Systems
Liviu Miclea, Technical University of Cluj-Napoca, Romania
Enyedi Szil?rd, Technical University of Cluj-Napoca, Romania
Gavril Toderean, Technical University of Cluj-Napoca, Romania
Alfredo Benso, Politecnico di Torino, Italy
Paolo Prinetto, Politecnico di Torino, Italy
pp. 952
Olivier Caty, Sun Microsystems, Sunnyvale, CA
Ismet Bayraktaroglu, Sun Microsystems, Sunnyvale, CA
Amitava Majumdar, Sun Microsystems, Sunnyvale, CA
Richard Lee, Microsoft Corporation, Mountain View, CA
John Bell, Sun Microsystems, Sunnyvale, CA
Lisa Curhan, Sun Microsystems, Sunnyvale, CA
pp. 961
Hardi Hungar, University of Dortmund, Germany; METAFrame Technologies GmbH, Germany
Tiziana Margaria, University of Dortmund, Germany; METAFrame Technologies GmbH, Germany
Bernhard Steffen, University of Dortmund, Germany
pp. 971
Rakesh N. Joshi, Texas Instruments, Inc. Sherman, Texas
Kenneth L. Williams, Texas Instruments, Inc. Sherman, Texas
Lee Whetsel, Texas Instruments, Inc. Sherman, Texas
pp. 981
Session 38: Lecture Series-P1500 Mergeable Cores
Francisco DaSilva, Synopsys, Inc., Mountain View, CA
Yervant Zorian, Virage Logic, Fremont, CA
Lee Whetsel, Texas Instruments, Dallas, TX
Karim Arabi, PMC Sierra, Burnaby, BC
Rohit Kapur, Synopsys, Inc., Mountain View, CA
pp. 988
Session 39: I/O Testing-Probe or Not?
Cheng Jia, Georgia Institute of Technology, Atlanta
Linda Milor, Georgia Institute of Technology, Atlanta
pp. 1023
Session 40: Quality
Brady Benware, LSI Logic Corporation, Gresham, OR
Chris Schuermyer, LSI Logic Corporation, Gresham, OR
Sreenevasan Ranganathan, LSI Logic Corporation, Gresham, OR
Robert Madge, LSI Logic Corporation, Gresham, OR
Prabhu Krishnamurthy, LSI Logic Corporation, Gresham, OR
Nagesh Tamarapalli, Mentor Graphics Corporation, Wilsonville, OR
Kun-Han Tsai, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
pp. 1031
Piet Engelke, Albert-Ludwigs-University
Ilia Polian, Albert-Ludwigs-University
Michel Renovell, LIRMM - UMII
Bernd Becker, Albert-Ludwigs-University
pp. 1051
Session 41: Test Data Compression
Masao Naruse, RENASAS, Technology corp., Kodaira-shi, Tokyo
Irith Pomeranz, Purdue University, W. Lafayette, IN
Sudhakar M. Reddy, University of Iowa, IA
Sandip Kundu, Intel corp., Austin, TX
pp. 1060
Harald Vranken, Philips Research, Digital Design & Test, The Netherlands
Friedrich Hapke, Philips Semiconductors, Germany
Soenke Rogge, Philips Semiconductors, Germany
Domenico Chindamo, Agilent Technologies, Italy
Erik Volkerink, Agilent Technologies, Palo Alto, CA
pp. 1069
Session 42: At-Speed Testing-New Solutions to Old Problems
Haluk Konuk, Broadcom Corporation, Santa Clara, California
Leon Xiao, Broadcom Corporation, Santa Clara, California
pp. 1105
Session 43: Extending IEEE 1149.1 Into The Backplane
Session 44: Infrastructure IP
L. Forli, IMT - Technop?le de Ch?teau Gombert, France; ST-Microelectronics, France
J. M. Portal, IMT - Technop?le de Ch?teau Gombert, France
D. N?, ST-Microelectronics, France
B. Borot, ST-Microelectronics, France
pp. 1129
Session 45: Analog Model-Based Testing
Zhen Guo, New Jersey Institute of Technology
Jacob Savir, New Jersey Institute of Technology
pp. 1155
Ram Voorakaranam, Ardext Technologies, Tucson, AZ
Randy Newby, Texas Instruments Inc., Tucson, AZ
Sasi Cherubal, Ardext Technologies, Tucson, AZ
Bob Cometta, Texas Instruments Inc., Tucson, AZ
Thomas Kuehl, Texas Instruments Inc., Tucson, AZ
David Majernik, Arctic Systems Inc, Burtonsville, MD
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
pp. 1174
Session 46: Test of Future Integrated Systems
Arun A. Joseph, University of Twente, The Netherlands
Hans G. Kerkhoff, University of Twente, The Netherlands
pp. 1182
Fei Su, Duke University, Durham, NC
Sule Ozev, Duke University, Durham, NC
Krishnendu Chakrabarty, Duke University, Durham, NC
pp. 1192
Mahim Mishra, Carnegie Mellon University, Pittsburgh, PA
Seth C. Goldstein, Carnegie Mellon University, Pittsburgh, PA
pp. 1201
Session 47: DFT Industrial Case Studies
Frank Poehl, Infineon Technologies AG, Munich, Germany
Matthias Beck, Infineon Technologies AG, Munich, Germany
Ralf Arnold, Infineon Technologies AG, Munich, Germany
Peter Muhmenthaler, Mentor Graphics Corporation, Wilsonville, OR
Nagesh Tamarapalli, Mentor Graphics Corporation, Wilsonville, OR
Mark Kassab, Mentor Graphics Corporation, Wilsonville, OR
Nilanjan Mukherjee, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
pp. 1211
David M. Wu, Intel Corporation
Mike Lin, Intel Corporation
Subhasish Mitra, Intel Corporation
Kee Sup Kim, Intel Corporation
Anil Sabbavarapu, Intel Corporation
Talal Jaber, Intel Corporation
Pete Johnson, Intel Corporation
Dale March, Intel Corporation
Greg Parrish, Intel Corporation
pp. 1229
Session 48: Interconnect Testing And BIST For FPGAS
Charles E. Stroud, Auburn University, AL
Keshia N. Leach, University of North Carolina at Charlotte
Thomas A. Slaughter, University of North Carolina at Charlotte
pp. 1258
Session 49: Board And System Test: Other Aspects of Board Test
Wouter Rijckaert, Philips Research Laboratories, Eindhoven, NL
Frans de Jong, Philips Research Laboratories, Eindhoven, NL
pp. 1277
Frans de Jong, Philips Research Eindhoven, NL
Leon van de Logt, Philips Research Eindhoven, NL
pp. 1278
Panel 1: How (In) Adequate is One-Time Testing?
Rubin A. Parekhji, Texas Instruments (India) Pvt. Ltd., Murugeshpalya, Bangalore
pp. 1279
Peter Ehlig, Texas Instruments, Inc., Stafford, Texas
pp. 1283
Yervant Zorian, Virage Logic Corporation, Fremont, California
pp. 1284
Panel 2: My DFT Is Better Than Yours... Is Better than None...
Panel 3: RF Test 101: Defining The Problem, Finding Solutions
Panel 4: The Confluence of Manufacturing Test And Design Validation
Prab Varma, Veritable Inc., Mountain View, CA
pp. 1292
Panel 5: PXI: A Solution For Board Functional Test?
Panel 6: Future ATE: Perspectives And Requirements
Lee Y. Song, Teradyne, Inc., Agoura Hills, CA
pp. 1300
Panel 7: Diagnosis In Modern Time-To-Volume-The Tip of The Iceberg
Robert Molyneaux, Sun Microsystems Inc., Austin, Texas
pp. 1303
Wu-Tung Cheng, Mentor Graphics Corporation, Wilsonville, Oregon
pp. 1305
Panel 8: Multi-GB/S IC Test Challenges And Solutions
Ulrich Schoettmer, Agilent Technologies, Boeblingen
Bernd Laquai, Agilent Technologies, Boeblingen
pp. 1310
Yi Cai, Agere Systems, Allentown, Pennsylvania
pp. 1312
Panel 9: DFM: The Real 90-NM Hurdle
Rob Aitken, Artisan Components, Sunnyvale, CA
pp. 1313
Rob Aitken, Artisan Components, Sunnyvale, CA
pp. 1314
Cliff Ma, Anchor Semiconductor, Inc., Santa Clara, California
pp. 1315
Jitendra B. Khare, Ample Communications, Inc. Fremont, CA
pp. 1317
Panel 10: Testing 3G-Controlled Systems: A Time to Rejoice or A Time to Feel Pain?
ITC 2002 Best Paper:
John Ferrario, IBM RF & Analog Test Development, Essex Junction, Vt
Randy Wolf, IBM RF & Analog Test Development, Essex Junction, Vt
Steve Moss, IBM RF & Analog Test Development, Essex Junction, Vt
pp. 1325
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