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International Test Conference 2002 (ITC'02)
Baltimore, MD, USA
October 07-October 10
ISBN: 0-7803-7543-2
Table of Contents
Introduction
EXECUTIVE PANEL: HOMEGROWN VERSUS COMMERCIAL SOLUTIONS FOR LOW-COST TEST
SPECIAL PANEL: TESTING THE TESTER
Rochit Rajsuman, Advantest America R & D Center, Inc.
pp. 27
Rochit Rajsuman, Advantest America R & D Center, Inc.
pp. 30
Keynote Address
Invited Address
SESSION 2: MEMORY TESTING
J. M. Portal, ICF/L2MP-UMR CNRS
L. Forli, ICF/L2MP-UMR CNRS and ST-Microelectronics
H. Aziza, ICF/L2MP-UMR CNRS and ST-Microelectronics
D. N?, ST-Microelectronics
pp. 31
Sau-Kwo Chiu, National Tsing Hua University
Jen-Chieh Yeh, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 37
SESSION 3: ADVANCES IN SOC TESTING
Yu Huang, Mentor Graphics Corporation
Sudhakar M. Reddy, University of Iowa
Wu-Tung Cheng, Mentor Graphics Corporation
Paul Reuter, Mentor Graphics Corporation
Nilanjan Mukherjee, Mentor Graphics Corporation
Chien-Chung Tsai, Mentor Graphics Corporation
Omer Samman, Mentor Graphics Corporation
Yahya Zaidan, Mentor Graphics Corporation
pp. 74
SESSION 4: DEFECT-ORIENTED TEST
Jaume Segura, University of the Balearic Islands
Ali Keshavarzi, Intel Corp
Jerry Soden, Sandia National Labs
Charles Hawkins, University of New Mexico
pp. 90
SESSION 5: HIGH-PERFORMANCE TIMING MEASUREMENTS
Mani Soma, University of Washington
Welela Haileselassie, University of Washington
Jessica Yan, University of Washington
Rajesh Raina, Motorola Inc.
pp. 120
SESSION 6: TEST DATA REDUCTION
Erik H. Volkerink, Stanford University and Agilent Laboratories
Ajay Khoche, Agilent Laboratories
Subhasish Mitra, Intel Corporation
pp. 154
SESSION 7: MEMORY DFT,BIST AND REPAIR
O. Hirabayashi, Toshiba Corporation
A. Suzuki, Toshiba Corporation
T. Yabe, Toshiba Corporation
A. Kawasumi, Toshiba Corporation
Y. Takeyama, Toshiba Corporation
K. Kushida, Toshiba Corporation
A. Tohata, Toshiba Microelectronics Corporation
N. Otsuka, Toshiba Corporation
pp. 164
Shigeki Tomishima, Mitsubishi Electric Corporation and Osaka University
Hiroaki Tanizaki, Mitsubishi Electric Engineering Co., Ltd.
Mitsutaka Niiro, Mitsubishi Electric Corporation
Masanao Maruta, Mitsubishi Electric Corporation
Hideto Hidaka, Mitsubishi Electric Corporation
T. Tada, Mitsubishi Electric Corporation
Kenji Gamo, Osaka University
pp. 170
Jayasanker Jayabalan, Infineon Technologies Asia Pacific Pte Ltd
Juraj Povazanec, Infineon Technologies Asia Pacific Pte Ltd
pp. 187
SESSION 8: DESIGN VALIDATION — NOVEL ATPG APPLICATIONS
Jacob A. Abraham, University of Texas at Austin
Vivekananda M. Vedula, University of Texas at Austin
Daniel G. Saab, Case Western Reserve University
pp. 194
Ganapathy Parthasarathy, University of California at Santa Barbara
Madhu K. Iyer, University of California at Santa Barbara
Tao Feng, University of California at Santa Barbara
Li-C. Wang, University of California at Santa Barbara
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
Magdy S. Abadir, Motorola
pp. 203
SESSION 9: NOVEL TECHNIQUES FOR DIAGNOSTICS
R. D. (Shawn) Blanton, Carnegie Mellon University
J. T. Chen, Carnegie Mellon University
R. Desineni, Carnegie Mellon University
K. N. Dwarakanath, Carnegie Mellon University
W. Maly, Carnegie Mellon University
T. J. Vogels, Carnegie Mellon University
pp. 233
Yasuo Sato, Hitachi, Ltd.
Iwao Yamazaki, Hitachi, Ltd.
Hiroki Yamanaka, Hitachi, Ltd.
Toshio Ikeda, Hitachi, Ltd.
Masahiro Takakura, Hitachi Engineering Co., Ltd.
pp. 242
Camelia Hora, Eindhoven University of Technology
Rene Segers, Philips Semiconductors
Stefan Eichenberger, Philips Semiconductors
Maurice Lousberg, Philips Research Labs
pp. 260
SESSION 10: CONNECTING DISCONNECTS
SESSION 11: TEST DATA COMPRESSION
Januz Rajki, Mentor Graphics Corporation
Jerzy Tyzer, Poznan University of Technology
Mark Kassab, Mentor Graphics Corporation
Nilanjan Mukherjee, Mentor Graphics Corporation
Rob Thompson, Mentor Graphics Corporation
Kun-Han Tsai, Mentor Graphics Corporation
Andre Hertwig, Mentor Graphics Corporation
Nagesh Tamarapalli, Mentor Graphics Corporation
Grzegorz Mrugalski, Poznan University of Technology
Geir Eide, Mentor Graphics Corporation
Jun Qian, Cisco Systems
pp. 301
SESSION 12: LECTURE SERIES — EMBEDDED IP FOR SOC INFRASTRUCTURE
SESSION 13: CHIP-LEVEL CROSSTALK IDENTIFICATION AND TESTING
Shahin Nazarian, University of Southern California
Hang Huang, University of Southern California
Suriyaprakash Natarajan, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A Breuer, University of Southern California
pp. 365
SESSION 14: ADVANCES IN FAULT SIMULATION AND TEST GENERATION
Jing-Jia Liou, University of California at Santa Barbara
Li-C. Wang, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
Jennifer Dworak, Texas A&M University
M. Ray Mercer, Texas A&M University
Rohit Kapur, Synopsys Inc.
Thomas W. Williams, Synopsys Inc.
pp. 407
SESSION 15: ADVENTURES IN INTERFACING
D. Gessel, Teradyne Integra Test Division
A. Slcoum, Massachusetts Institute of Technology
A. Sprunt, Massachusetts Institute of Technology
S. Ziegenhagen, Teradyne Connection Systems
pp. 417
Kenichi Kataoka, University of Tokyo
Toshihiro Itoh, University of Tokyo
Katsuya Okumura, University of Tokyo
Tadatomo Suga, University of Tokyo
pp. 424
SESSION 16: DFT TESTERS
J.S. Davis, Georgia Institute of Technology
D.C. Keezer, Georgia Institute of Technology
pp. 438
Mike Mayberry, Intel Corporation
John Johnson, Intel Corporation
Navid Shahriari, Intel Corporation
Mike Tripp, Intel Corporation
pp. 456
SESSION 17: PRODUCTION TEST AUTOMATION
David Turner, Portland State University
David Abercrombie, LSI Logic
James McNames, Portland State University
Robert Daasch, Portland State University
Robert Madge, LSI Logic
pp. 464
David Williams, Dell Computer Corporation and University of Texas at Austin
Anthony P. Ambler, University of Texas at Austin
pp. 482
SESSION 18: SOFT AND HARD FAILURE ANALYSIS AND ON-LINE TESTING
Yi Zhao, University of California at San Diego
Li Chen, University of California at San Diego
Sujit Dey, University of California at San Diego
pp. 491
A. Benso, Politecnico di Torino
S. Di Carlo, Politecnico di Torino
G. Di Natale, Politecnico di Torino
P. Prinetto, Politecnico di Torino
pp. 500
SESSION 19: SOC BENCHMARKS
SESSION 20: APPLICATION SERIES — HIGH-SPEED TEST INTERFACES
SESSION 21: TEST AND DEBUG OF MICROPROCESSORS
B. Bailey, Motorola Inc.
A. Metayer, Motorola Inc.
B. Svrcek, Motorola Inc.
N. Tendolkar, Motorola Inc.
E. Wolf, Motorola Inc.
E. Fiene, Motorola Inc.
M. Alexander, Motorola Inc.
R. Woltenberg, Motorola Inc.
R. Raina, Motorola Inc.
pp. 574
SESSION 22: FPGA TESTING
Charles Stroud, University of North Carolina at Charlotte
Jeremy Nall, University of North Carolina at Charlotte
Matthew Lashinsky, University of North Carolina at Charlotte
Miron Abramovici, Agere Systems
pp. 618
SESSION 23: LECTURE SERIES — SILICON DEBUG
Bart Vermeulen, Philips Research Laboratories
Tom Waayers, Philips Research Laboratories
Sandeep Kumar Goel, Philips Research Laboratories
pp. 638
Xinli Gu, Cisco Systems, Inc.
Weili Wang, Cisco Systems, Inc.
Kevin Li, Cisco Systems, Inc.
Heon Kim, Cisco Systems, Inc.
Sung S. Chung, Cisco Systems, Inc.
pp. 648
SESSION 24: DATA ANALYSIS AND YIELD MODEL VALIDATION
R. Madge, LSI Logic Corporation
B.H. Goh, LSI Logic Corporation
V. Rajagopalan, LSI Logic Corporation
C. Macchietto, LSI Logic Corporation
R. Daasch, Portland State University
C. Schuermyer, Portland State University
C. Taylor, Portland State University
D. Turner, Portland State University
pp. 673
Minh Quach, Agilent Technologies Company
Tuan Pham, Agilent Technologies Company
Tim Figal, Agilent Technologies Company
Bob Kopitzke, Agilent Technologies Company
Pete O?Neill, Agilent Technologies Company
pp. 683
SESSION 25: JITTER TESTING IN MULTI-GIGAHERTZ DIGITAL SYSTEMS
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.
Mani Soma, University of Washington
Masahiro Ishida, Advantest Laboratories, Ltd.
Hirobumi Musha, Advantest Corporation
Louis Malarsie, Agere Systems
pp. 717
SESSION 26: EFFICIENT APPROACHES TO SOC TESTING
Ishwar Parulkar, Sun Microsystems, Inc.
Thomas Ziaja, Sun Microsystems, Inc.
Rajesh Pendurkar, Sun Microsystems, Inc.
Anand D'Souza, Sun Microsystems, Inc.
Amitava Majumdar, Sun Microsystems, Inc.
pp. 726
Sungbae Hwang, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
pp. 736
SESSION 27: 1149.1 VERIFICATION AND VALIDATION
Sezer G?ren, University of California at Santa Cruz
F. Joel Ferguson, University of California at Santa Cruz
pp. 773
SESSION 28: SCAN STITCHING
David Berthelot, Magma Design Automation, Inc.
Samit Chaudhuri, Magma Design Automation, Inc.
Hamid Savoj, Magma Design Automation, Inc.
pp. 781
L. Guiller, Synopsys, Inc.
F. Neuveux, Synopsys, Inc.
S. Duggirala, Synopsys, Inc.
R. Chandramouli, Synopsys, Inc.
R. Kapur, Synopsys, Inc.
pp. 788
Y. Bonhomme, Universit? Montpellier II /CNRS
P. Girard, Universit? Montpellier II /CNRS
C. Landrault, Universit? Montpellier II /CNRS
S. Pravossoudovitch, Universit? Montpellier II /CNRS
pp. 796
Frank te Beest, University of Twente
Ad Peeters, Philips Research Laboratories
Marc Verra, Philips Research Laboratories
Kees van Berkel, Philips Research Laboratories and Eindhoven University of Technology
Hans Kerkhoff, University of Twente
pp. 804
SESSION 29: DFT FOR MANUFACTURING PROBLEMS
M.B. Santos, IST/Inesc-id
I.C. Teixeira, IST/Inesc-id
J.P. Teixeira, IST/Inesc-id
S. Manich, Università Politecnica de Catalunya
R. Rodriquez, Università Politecnica de Catalunya
J. Figueras, Università Politecnica de Catalunya
pp. 814
Ozgur Sinanoglu, University of California at San Diego
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 844
SESSION 30: MIXED-SIGNAL TEST TECHNIQUES
M. Stancic, University of Twente
L. Fang, University of Twente
M. H. H. Weusthof, University of Twente
R. M. W. Tijink, University of Twente
H. G. Kerkhoff, University of Twente
pp. 861
Gunter Krampl, Infineon Technologies Microelectronic Design Centers Austria GmbH
Marco Rona, Infineon Technologies Microelectronic Design Centers Austria GmbH
Hermann Tauber, Infineon Technologies Microelectronic Design Centers Austria GmbH
pp. 870
SESSION 31: GO-FAST ATE!
Toshiyuki Okayasu, ADVANTEST Corporation
Masakatsu Suda, ADVANTEST Corporation
Kazuhiro Yamamoto, ADVANTEST Corporation
pp. 894
SESSION 32: SYSTEM TEST DESIGN, BIST AND SYSTEM VERIFICATION
Andrea Baldini, Politecnico di Torino
Alfredo Benso, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
Sergio Mo, Magneti Marelli Electronic Systems
Andrea Taddei, Magneti Marelli Electronic Systems
pp. 930
Liviu Miclea, Technical University of Cluj-Napoca
Enyedi Szil?rd, Technical University of Cluj-Napoca
Alfredo Benso, Politecnico di Torino
pp. 940
SESSION 33: ADVANCES IN IDDX
B. Alorda, University Illes Balears
M. Rosales, University Illes Balears
J. Soden, Sandia National Laboratories
C. Hawkins, University of New Mexico
J. Segura, University Illes Balears
pp. 947
David I. Bergman, National Institute of Standards and Technology
Hans Engler, Georgetown University
pp. 954
Bram Kruseman, Philips Research Laboratories
Stefan van den Oetelaar, Philips Research Laboratories
Josep Rius, DEE of Universitat Politecnica de Catalunya
pp. 964
SESSION 34: DELAY-TEST
Manish Sharma, University of Illinois at Urbana Champaign
Janak H. Patel, University of Illinois at Urbana Champaign
pp. 974
Xiao Liu, Virginia Tech
Michael Hsiao, Virginia Tech
Sreejit Chakravarty, Virginia Tech and Intel Corporation
Paul J. Thadikaran, Virginia Tech and Intel Corporation
pp. 983
SESSION 35: EMBEDDED TEST FOR ANALOG AND DIGITAL
SESSION 36: MAXIMIZING TEST EFFECTIVENESS AND MINIMIZING COST
Aubin Roy, LogicVision (Canada), Inc.
Stephen Sunter, LogicVision (Canada), Inc.
Alessandra Fudoli, STMicroelectronics
Davide Appello, STMicroelectronics
pp. 1031
SESSION 37: BOARD TEST AND BIST FOR MEMS
SESSION 38: DEBUG AND DIAGNOSIS
SESSION 39: DELAY-TEST: PRACTICAL EXPERIENCE AND SOLUTIONS
Jayashree Saxena, Texas Instruments Inc.
Kenneth M. Butler, Texas Instruments Inc.
John Gatt, Texas Instruments Inc.
R Raghuraman, Texas Instruments Inc.
Sudheendra Phani Kumar, Texas Instruments Inc.
Supatra Basu, Texas Instruments Inc.
David J. Campbell, Texas Instruments Inc.
John Berech, Texas Instruments Inc.
pp. 1120
SESSION 40: RF TESTING
Koji Asami, Advantest Gunma R&D Center
Yasuo Furukawa, Advantest Gunma R&D Center
Michael Purtell, Advantest America, Inc.
Motoo Ueda, Advantest America, Inc.
Karl Watanabe, Advantest America, Inc.
Toshifumi Watanabe, Advantest America, Inc.
pp. 1140
John Ferrario, IBM RF & Analog Test Development
Randy Wolf, IBM RF & Analog Test Development
Steve Moss, IBM RF & Analog Test Development
pp. 1151
SESSION 41: TEST RESOURCE PARTITIONING
Rainer Dorsch, University of Stuttgart
Ram?n Huerta Rivera, University of Stuttgart
Hans-Joachim Wunderlich, University of Stuttgart
Martin Fischer, Agilent Technologies
pp. 1169
Mohsen Nahvi, University of British Columbia
Andr? Ivanov, University of British Columbia
Resve Saleh, University of British Columbia
pp. 1176
PANEL 1: CAN SYSTEM TEST AND IC TEST LEARN FROM EACH OTHER?
David Williams, Dell Computer Corporation and University of Texas at Austin
pp. 1185
Rochit Rajsuman, Advantest America R & D Center Inc.
pp. 1186
Anthony P. Ambler, University of Texas at Austin
pp. 1188
PANEL 2: TAPS ALL OVER MY CHIPS
Steven F. Oakland, IBM Microelectronic Division
pp. 1192
PANEL 3: CAN SCAN ACHIEVE THE QUALITY LEVEL WE ARE LOOKING FOR?
PANEL 4: MIXED-SIGNAL BIST: FACT OR FICTION?
Arnold Frisch, Integrated Measurement Systems™, Inc. A Credence Company
pp. 1201
PANEL 5: MISSION POSSIBLE?: AN OPEN ATE TESTER ARCHITECTURE
Paul F. Scrivens, Third Millennium Test Solutions
pp. 1208
PANEL 6: THE IMPACTS OF OUTSOURCING ON TEST
PANEL 7: TEST AND REPAIR OF COMMODITY AND EMBEDDED FLASH MEMORIES
PANEL 8: TESTING HIGHLY INTEGRATED CIRCUITS AND SYSTEMS USING A LOW-COST TESTER:HOW TO OVERCOME THE CHALLENGE?
PANEL 9: MULTI-GHZ ERA: TEST CHALLENGES AND SOLUTIONS
C. Hawkins, University of New Mexico
J. Segura, Balearic Islands University
pp. 1228
PANEL 10: BOARD TEST AND ITC: WHAT DOES THE FUTURE HOLD?
Gordon D Robinson, Third Millennium Test Solutions
pp. 1236
Kenneth P. Parker, Agilent Technologies
pp. 1238
2001 ITC BEST PAPER:
W. Robert Daasch, Portland State University
Kevin Cota, Portland State University
James McNames, Portland State University
Robert Madge, LSI Logic Corporation
pp. 1240
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