- I
- ITC
- 2001
- International Test Conference 2001 (ITC'01)
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| | | | Bibliographic References | | | |
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International Test Conference 2001 (ITC'01) Baltimore, Maryland October 30-November 01 ISBN: 0-7803-7171-2 Table of Contents
 | INTRODUCTORY SECTION |
| SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET? |
| SPECIAL PANEL: STRUCTURED TEST: THEN AND NOW |
| SESSION 1: PLENARY |
| SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST |
| SESSION 3: BIST MEDLEY |
Xiaoming Yu, University of Illinois at Urbana-Champaign pp. 64
| SESSION 4: HOW CAN WE INPROVE IDDQ TESTING FOR DSM/VDSM? |
| SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING |
| SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE |
| SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS |
| SESSION 8: DFT INNOVATIONS |
| SESSION 9: ON-LINE TEST |
| SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS |
| SESSION 11: TESTING ABOVE A GIGAHERTZ |
| SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES |
| SESSION 13: HIGH-QUALITY TEST |
| SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES |
| SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS |
| SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES |
| SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS |
| SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES |
| SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING |
| SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS |
| SESSION 21: MICROPROCESSOR TESTING |
| SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT |
Sergio MO, Magneti Marelli Electronic Systems pp. 600
| SESSION 23: DELAY TEST |
| SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION |
| SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL |
| SESSION 26: ATE HW: CONQUERING THOSE STUBBORN TEST PROBLEMS |
| SESSION 27: ADVANCES IN SCAN TESTING |
| SESSION 28: MEMORY TESTING |
| SESSION 29: INCREASING DESIGN VALIDATION COVERAGE |
| SESSION 30: PLL AND JITTER TESTING |
| SESSION 31: NEW IDEAS FOR BIST TPG |
| SESSION 32: TEST AUTOMATION, IMPROVING IC TEST EFFICIENCY |
| SESSION 33: FPGA TESTING |
| SESSION 34: RF TESTING |
| SESSION 35: EMBEDDED MEMORIES TEST AND REPAIR |
| SESSION 36: LECTURE SERIES mdash; LOGIC BIST CASE STUDIES |
| SESSION 37: ADVANCED METHODS IN EMBEDDED CORE TEST |
| SESSION 38: HOW COULD WE MODEL AND TEST VDSM DEFECTS |
| SESSION 39: PRACTICAL TEST GENERATION TECHNIQUES |
| SESSION 40: DELVING INTO FACTORS AFFECTING MANUFACTURING COST |
| SESSION 41: ATE HARDWARE: FROM GIGAHERTZ TO TERAHERTZ |
Q. Zhou, Georgia Institute of Technology
C. Bair, Semiconductor Products Group
J. Kuan, Semiconductor Products Group pp. 1143
| PANEL 1: SEARCHING FOR COMMON GROUND BETWEEN LOW-COST AND HIGH-PERFORMANCE ATE SYSTEMS |
| PANEL 2: OPEN MICROPHONE — WANTED: NEW TEST DIRECTIONS AND PRACTICAL TEST BOTTLENECKS |
| PANEL 3: CAN ANYONE STILL AFFORD SYSTEM TEST? |
| PANEL 4: THE CHALLENGES OF MANAGING TEST |
| PANEL 5: IS STRIP TESTING THE NEXT ADVANCE FOR SEMICONDUCTOR TEST? |
| PANEL 6: SYSTEM-IN-A-PACKAGE IS COMING TO CONSUMER PRODUCTS — IS TEST READY? |
| PANEL 7: AC SCAN: MICROPROCESSORS ARE READY...BUT WHERE IS THE INFRASTRUCTURE? |
| PANEL 8: DFT-CORRECT BY CONSTRUCTION OR MAKE IT WORK? |
| PANEL 9: LOWERING THE COST OF TEST: ATPG VS. BIST |
| PANEL 10: STANDARDIZED TESTING OF AC-COUPLED ICS ON HIGH-SPEED BOARDS AND SYSTEMS |
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