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International Test Conference 2001 (ITC'01)
Baltimore, Maryland
October 30-November 01
ISBN: 0-7803-7171-2
Table of Contents
INTRODUCTORY SECTION
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
Lori Watrous-deVersterre, Mentor Graphics Corporation
pp. 27
SPECIAL PANEL: STRUCTURED TEST: THEN AND NOW
SESSION 1: PLENARY
null
SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST
null
Stephen Sunter, LogicVision, Inc.
Ken Filliter, National Semiconductor Corp.
Joe Woo, Lockheed Martin - EPI
Pat McHugh, Lockheed Martin - EPI
pp. 38
Young Kim, Agilent Technologies
Benny Lai, Agilent Technologies
Kenneth P. Parker, Agilent Technologies
Jeff Rearick, Agilent Technologies
pp. 46
SESSION 3: BIST MEDLEY
null
Jongshin Shin, University of Illinois at Urbana-Champaign
Xiaoming Yu, University of Illinois at Urbana-Champaign
Elizabeth M. Rudnick, University of Illinois at Urbana-Champaign
Miron Abramovici, Agere Systems
pp. 64
SESSION 4: HOW CAN WE INPROVE IDDQ TESTING FOR DSM/VDSM?
null
W. Robert Daasch, Portland State University
Kevin Cota, Portland State University
James McNames, Portland State University
Robert Madge, LSI Logic Corporation
pp. 92
Bram Kruseman, Philips Research Laboratories
Rutger van Veen, Philips Research Laboratories
Kees van Kaam, Philips Research Laboratories
pp. 101
SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING
null
Bart Vermeulen, Philips Research Laboratories
Steven Oostdijk, Philips Semiconductors North America
Frank Bouwman, Philips Semiconductors North America
pp. 121
SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE
null
Andrew Moran, Galois Connections Inc.
Jim Teisher, Galois Connections Inc.
Andrew Gill, Galois Connections Inc.
Emir Pasalic, Oregon Graduate Institute
John Veneruso, Credence Systems Corporation
pp. 148
SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS
null
Roderick McConnell, Infineon Technologies,
Rochit Rajsuman, Advantest America
Erik Nelson, IBM Microelectronics
Jeffrey Dreibelbis, IBM Microelectronics
pp. 163
Yoshihiro Nagura, Mitsubishi Electric Corp.
Michael Mullins, Mitsubishi Electronics America, Inc.
Anthony Sauvageau, Mitsubishi Electronics America, Inc.
Yoshinori Fujiwara, Mitsubishi Electric Corp.
Katsuya Furue, Mitsubishi Electric Corp.
Ryuji Ohmura, Mitsubishi Electric Corp.
Tatsunori Komoike, Mitsubishi Electric Corp.
Takenori Okitaka, Mitsubishi Electric Corp.
Tetsushi Tanizaki, Mitsubishi Electric Corp.
Katsumi Dosaka, Mitsubishi Electric Corp.
Kazutami Arimito, Mitsubishi Electric Corp.
Yukiyoshi Koda, Mitsubishi Electric Corp.
Tetsuo Tada, Mitsubishi Electric Corp.
pp. 182
SESSION 8: DFT INNOVATIONS
null
Kee Sup Kim, Intel Corporation
Rathish Jayabharathi, Intel Corporation
Craig Carstens, Intel Corporation
Praveen Vishakantaiah, Intel Corporation
Derek Feltham, Intel Corporation
Adrian Carbine, Intel Corporation
pp. 188
SESSION 9: ON-LINE TEST
null
Silvia CHIUSANO, Politecnico di Torino
Giorgio DI NATALE, Politecnico di Torino
Paolo PRINETTO, Politecnico di Torino
Franco BIGONGIARI, Aurelia Microelectronica
pp. 250
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS
null
John T Chen, Carnegie Mellon University
Jitendra Khare, Intel Corporation
Ken Walker, Intel Corporation
Saghir Shaikh, Intel Corporation
Janusz Rajski, Mentor Graphics Corporation
Wojciech Maly, Carnegie Mellon University
pp. 258
Thomas Bartenstein, IBM Microelectronics Division
Douglas Heaberlin, IBM Microelectronics Division
Leendert Huisman, IBM Microelectronics Division
David Sliwinski, IBM Microelectronics Division
pp. 287
SESSION 11: TESTING ABOVE A GIGAHERTZ
null
Ming-Jun Hsiao, National Tsing-Hua University
Jing-Reng Huang, National Tsing-Hua University
Shao-Shen Yang, National Tsing-Hua University
Tsin-Yuan Chang, National Tsing-Hua University
pp. 315
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.
Mani Soma, University of Washington
Jim Nissen, Motorola Inc.
David Halter, Motorola Inc.
Rajesh Raina, Motorola Inc.
Masahiro Ishida, Advantest Laboratories, Ltd.
pp. 323
SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES
null
SESSION 13: HIGH-QUALITY TEST
null
SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES
null
Abhishek Singh, University of Maryland, Baltimore County
Chintan Patel, University of Maryland, Baltimore County
Shirong Liao, University of Maryland, Baltimore County
Jim Plusquellic, University of Maryland, Baltimore County
Anne Gattiker, IBM Austin Research Lab
pp. 395
SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS
null
G. Dajee, Schlumberger Probe Systems
N. Goldblatt, Schlumberger Probe Systems
T. Lundquist, Schlumberger Probe Systems
S. Kasapi, Schlumberger Probe Systems
K. Wilsher, Schlumberger Probe Systems
pp. 433
SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES
null
Michael Kessler, IBM Deutschland Entwicklung GmbH
Gundolf Kiefer, University of Stuttgart
Jens Leenstra, IBM Deutschland Entwicklung GmbH
Knut Schünemann, IBM Deutschland Entwicklung GmbH
Thomas Schwarz, University of Stuttgart
Hans-Joachim Wunderlich, University of Stuttgart
pp. 461
SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS
null
SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES
null
Mamoru Tamba, Agilent Technologies Japan, Ltd
Atsushi Shimizu, Agilent Technologies Japan, Ltd
Hideharu Munakata, Agilent Technologies Japan, Ltd
Takanori Komuro, Agilent Technologies Japan, Ltd
pp. 512
SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING
null
Ozgur Sinanoglu, University of California, San Diego
Alex Orailoglu, University of California, San Diego
pp. 521
Frank F. Hsu, Texas Instruments Inc.
Kenneth M. Butler, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 538
SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS
null
Liang-Chi Chen, University of Southern California, Los Angeles
T. M. Mak, Intel Corporation
Melvin A. Breuer, University of Southern California, Los Angeles
Sandeep K. Gupta, University of Southern California, Los Angeles
pp. 548
Angela Krstic, University of California, Santa Barbara
Jing-Jia Liou, University of California, Santa Barbara
Yi-Min Jiang, Synopsys, Inc.
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
pp. 558
SESSION 21: MICROPROCESSOR TESTING
null
Don Douglas Josephson, Hewlett-Packard Company
Steve Poehlman, Intel Corporation
Vincent Govan, Hewlett-Packard Company
Clint Mumford, Hewlett-Packard Company
pp. 578
SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT
null
Andrea BALDINI, Politecnico di Torino
Alfredo BENSO, Politecnico di Torino
Paolo PRINETTO, Politecnico di Torino
Sergio MO, Magneti Marelli Electronic Systems
Andrea TADDEI, Magneti Marelli Electronic Systems
pp. 600
Robert Tappe, AUDI AG Ingolstadt, Germany
Dietmar Ehrhardt, University of Siegen, Germany
pp. 609
Bill Eklow, Cisco Systems Inc.
Richard Sedmak, Self Test Services, voice net
Dan Singletary, Cisco Systems Inc.
Toai Vo, Cisco Systems Inc.
pp. 615
SESSION 23: DELAY TEST
null
Manish Sharma, University of Illinois at Urbana Champaign
Janak H. Patel, University of Illinois at Urbana Champaign
pp. 634
S. Padmanaban, Southern Illinois University
M. Michael, Southern Illinois University
S. Tragoudas, Southern Illinois University
pp. 642
SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION
null
Lei Xu, Tsinghua University
Yihe Sun, Tsinghua University
Hongyi Chen, Tsinghua University
pp. 652
Tsung-Chu Huang, National Cheng Kung University
Kuen-Jong Lee, National Cheng Kung University
pp. 660
SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL
null
SESSION 26: ATE HW: CONQUERING THOSE STUBBORN TEST PROBLEMS
null
Chintan Patel, University of Maryland, Baltimore County
Fidel Muradali, University of Maryland, Baltimore County
Jim Plusquellic, University of Maryland, Baltimore County
pp. 704
SESSION 27: ADVANCES IN SCAN TESTING
null
On RTL Scan Design (Abstract)
Yu Huang, University of Iowa, Iowa City
Chien-Chung Tsai, Mentor Graphics Corporation
Nilanjan Mukherjee, Mentor Graphics Corporation
Omer Samman, Mentor Graphics Corporation
Dan Devries, Mentor Graphics Corporation
Wu-Tung Cheng, Mentor Graphics Corporation
Sudhakar M. Reddy, University of Iowa, Iowa City
pp. 728
Harald Vranken, Philips Research Laboratories
Tom Waayers, Philips Research Laboratories
Hervé Fleury, Philips Semiconductors
David Lelouvier, Philips Semiconductors
pp. 738
Carl Barnhart, IBM Microelectronics
Vanessa Brunkhorst, IBM Microelectronics
Frank Distler, IBM Microelectronics
Owen Farnsworth, IBM Microelectronics
Brion Keller, IBM Microelectronics
Bernd Koenemann, IBM Microelectronics
pp. 748
SESSION 28: MEMORY TESTING
null
Jin-Fu Li, National Tsing Hua University
Kuo-Liang Cheng, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 758
Harold Pilo, IBM Microelectronics Division
R. Dean Adams, IBM Microelectronics Division
Robert E. Busch, IBM Microelectronics Division
Erik A. Nelson, IBM Microelectronics Division
George E. Rudgers, IBM Microelectronics Division
pp. 776
Zaid Al-Ars, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Jens Braun, Infineon Technologies AG
Detlev Richter, Infineon Technologies AG
pp. 783
SESSION 29: INCREASING DESIGN VALIDATION COVERAGE
null
Alessandro Fin, Universit? di Verona, Italy
Franco Fummi, Universit? di Verona, Italy
Graziano Pravadelli, Universit? di Verona, Italy
pp. 821
SESSION 30: PLL AND JITTER TESTING
null
SESSION 31: NEW IDEAS FOR BIST TPG
null
C. V. Krishna, University of Texas, Austin
Abhijit Jas, University of Texas, Austin
Nur A. Touba, University of Texas, Austin
pp. 885
Hua-Guo Liang, University of Stuttgart, Germany
Sybille Hellebrand, University of Innsbruck, Austria
Hans-Joachim Wunderlich, University of Stuttgart, Germany
pp. 894
SESSION 32: TEST AUTOMATION, IMPROVING IC TEST EFFICIENCY
null
Ajay Khoche, Agilent Technologies Inc.
Rohit Kapur, Synopsys Inc.
David Armstrong, Agilent Technologies Inc.
T. W. Williams, Synopsys Inc.
Mick Tegethoff, Agilent Technologies Inc.
Jochen Rivoir, Agilent Technologies Inc.
pp. 916
SESSION 33: FPGA TESTING
null
Ian G. Harris, University of Massachusetts at Amherst
Premachandran R. Menon, University of Massachusetts at Amherst
Russell Tessier, University of Massachusetts at Amherst
pp. 932
SESSION 34: RF TESTING
null
SESSION 35: EMBEDDED MEMORIES TEST AND REPAIR
null
Peter Jakobsen, IBM Microelectronics Division
Jeffrey Dreibelbis, IBM Microelectronics Division
Gary Pomichter, IBM Microelectronics Division
Darren Anand, IBM Microelectronics Division
John Barth, IBM Microelectronics Division
Michael Nelms, IBM Microelectronics Division
Jeffrey Leach, IBM Microelectronics Division
George Belansek, IBM Microelectronics Division
pp. 975
Volker Schöber, Infineon Technologies AG
Steffen Paul, Infineon Technologies AG
Olivier Picot, Infineon Technologies AG
pp. 995
SESSION 36: LECTURE SERIES mdash; LOGIC BIST CASE STUDIES
null
Xinli Gu, Cisco Systems, Inc.
Sung Soo Chung, Cisco Systems, Inc.
Frank Tsang, Cisco Systems, Inc.
Jan A. Tofte, Mentor Graphics Corp.
Hamid Rahmanian, Mentor Graphics Corp.
pp. 1002
John Braden, Sun Microsystems, Inc.
Qing Lin, Sun Microsystems, Inc.
Brian Smith, Sun Microsystems, Inc.
pp. 1017
SESSION 37: ADVANCED METHODS IN EMBEDDED CORE TEST
null
SESSION 38: HOW COULD WE MODEL AND TEST VDSM DEFECTS
null
M. Renovell, Universit? de Montpellier II
J.M. Gallière, Universit? de Montpellier II
F. Azaïs, Universit? de Montpellier II
Y. Bertrand, Universit? de Montpellier II
pp. 1039
SESSION 39: PRACTICAL TEST GENERATION TECHNIQUES
null
Yong Chang Kim, University of Wisconsin-Madison
Vishwani D. Agrawal, CAS Res. Lab, Agere Systems
Kewal K. Saluja, University of Wisconsin-Madison
pp. 1078
SESSION 40: DELVING INTO FACTORS AFFECTING MANUFACTURING COST
null
Erik H. Volkerink, Agilent Laboratories; MESA Research Institute
Ajay Khoche, Agilent Laboratories
Linda A. Kamas, Agilent Laboratories
Jochen Rivoir, Agilent Laboratories
Hans G. Kerkhoff, MESA Research Institute
pp. 1098
SESSION 41: ATE HARDWARE: FROM GIGAHERTZ TO TERAHERTZ
null
Atsushi Oshima, Schlumberger Semiconductor Solutions
John Poniatowski, Schlumberger Semiconductor Solutions
Toshihiro Nomura, Schlumberger Semiconductor Solutions
pp. 1128
D.C. Keezer, Georgia Institute of Technology
Q. Zhou, Georgia Institute of Technology
C. Bair, Semiconductor Products Group
J. Kuan, Semiconductor Products Group
B. Poole, Semiconductor Products Group
pp. 1143
PANEL 1: SEARCHING FOR COMMON GROUND BETWEEN LOW-COST AND HIGH-PERFORMANCE ATE SYSTEMS
Gordon D Robinson, Third Millennium Test Solutions
pp. 1156
PANEL 2: OPEN MICROPHONE — WANTED: NEW TEST DIRECTIONS AND PRACTICAL TEST BOTTLENECKS
PANEL 3: CAN ANYONE STILL AFFORD SYSTEM TEST?
PANEL 4: THE CHALLENGES OF MANAGING TEST
Atul Goel, Agilent Technologies, Inc.
pp. 1161
John L. Harris, IBM Microelectronics
pp. 1162
Hwei-tsu Ann Luh, Taiwan Semiconductor Manufacturing Company
pp. 1163
PANEL 5: IS STRIP TESTING THE NEXT ADVANCE FOR SEMICONDUCTOR TEST?
PANEL 6: SYSTEM-IN-A-PACKAGE IS COMING TO CONSUMER PRODUCTS — IS TEST READY?
Larry Gilg, Die Products Consortium
pp. 1169
PANEL 7: AC SCAN: MICROPROCESSORS ARE READY...BUT WHERE IS THE INFRASTRUCTURE?
PANEL 8: DFT-CORRECT BY CONSTRUCTION OR MAKE IT WORK?
PANEL 9: LOWERING THE COST OF TEST: ATPG VS. BIST
Scott Davidson, Sun Microsystems Inc.
pp. 1182
PANEL 10: STANDARDIZED TESTING OF AC-COUPLED ICS ON HIGH-SPEED BOARDS AND SYSTEMS
2000 ITC BEST PAPER:
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