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International Test Conference 2001 (ITC'01)
Terabit-per-second Automated Digital Testing
Baltimore, Maryland
October 30-November 01
ISBN: 0-7803-7171-2
D.C. Keezer, Georgia Institute of Technology
Q. Zhou, Georgia Institute of Technology
C. Bair, Semiconductor Products Group
J. Kuan, Semiconductor Products Group
B. Poole, Semiconductor Products Group
This paper describes a test application for an IC with over 200 logic signals each carrying multiple-gigahertz data. An aggregate data rate approaching a terabit-per-second is attained during the test. A high pin-count automated test system with a maximum frequency of 1.33 Gbps DNRZ is used as a development platform. Data rate tripling logic is added to the system to produce stimuli signals each with DNRZ rates up to 4 Gbps. High-speed sampling circuits are added to capture the device output signals at these same frequencies. Several example measurements illustrate the signal quality that is achieved. The extraordinary performance exhibited by this application represents one of the most challenging digital test applications reported to-date, and foreshadows expectations for future automated test equipment.
Citation:
D.C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole, "Terabit-per-second Automated Digital Testing," itc, pp.1143, International Test Conference 2001 (ITC'01), 2001
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