This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
International Test Conference 2001 (ITC'01)
Test cost reduction by at-speed BISR for embedded DRAMs
Baltimore, Maryland
October 30-November 01
ISBN: 0-7803-7171-2
ASCII Text
x 
 
Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinori Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimito, Yukiyoshi Koda, Tetsuo Tada, "Test cost reduction by at-speed BISR for embedded DRAMs," 2012 IEEE International Test Conference, pp. 182, International Test Conference 2001 (ITC'01), 2001.
 
 
BibTex
x
 
@article{ 10.1109/TEST.2001.966632,
author = {Yoshihiro Nagura and Michael Mullins and Anthony Sauvageau and Yoshinori Fujiwara and Katsuya Furue and Ryuji Ohmura and Tatsunori Komoike and Takenori Okitaka and Tetsushi Tanizaki and Katsumi Dosaka and Kazutami Arimito and Yukiyoshi Koda and Tetsuo Tada},
title = {Test cost reduction by at-speed BISR for embedded DRAMs},
journal ={2012 IEEE International Test Conference},
volume = {0},
year = {2001},
isbn = {0-7803-7171-2},
pages = {182},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2001.966632},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - 2012 IEEE International Test Conference
TI - Test cost reduction by at-speed BISR for embedded DRAMs
SN - 0-7803-7171-2
SP
EP
A1 - Yoshihiro Nagura,
A1 - Michael Mullins,
A1 - Anthony Sauvageau,
A1 - Yoshinori Fujiwara,
A1 - Katsuya Furue,
A1 - Ryuji Ohmura,
A1 - Tatsunori Komoike,
A1 - Takenori Okitaka,
A1 - Tetsushi Tanizaki,
A1 - Katsumi Dosaka,
A1 - Kazutami Arimito,
A1 - Yukiyoshi Koda,
A1 - Tetsuo Tada,
PY - 2001
KW - null
VL - 0
JA - 2012 IEEE International Test Conference
ER -
 
Yoshihiro Nagura, Mitsubishi Electric Corp.
Michael Mullins, Mitsubishi Electronics America, Inc.
Anthony Sauvageau, Mitsubishi Electronics America, Inc.
Yoshinori Fujiwara, Mitsubishi Electric Corp.
Katsuya Furue, Mitsubishi Electric Corp.
Ryuji Ohmura, Mitsubishi Electric Corp.
Tatsunori Komoike, Mitsubishi Electric Corp.
Takenori Okitaka, Mitsubishi Electric Corp.
Tetsushi Tanizaki, Mitsubishi Electric Corp.
Katsumi Dosaka, Mitsubishi Electric Corp.
Kazutami Arimito, Mitsubishi Electric Corp.
Yukiyoshi Koda, Mitsubishi Electric Corp.
Tetsuo Tada, Mitsubishi Electric Corp.
The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7mm2 about 2% of conventional SOC devices. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM functional test time was reduced about 20% less than conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with conventional method.
Citation:
Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinori Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimito, Yukiyoshi Koda, Tetsuo Tada, "Test cost reduction by at-speed BISR for embedded DRAMs," itc, pp.182, International Test Conference 2001 (ITC'01), 2001
Usage of this product signifies your acceptance of the Terms of Use.