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International Test Conference 2000 (ITC'00)
Atlantic City, NJ, USA
October 03-October 05
ISBN: 0-7803-6546-1
Table of Contents
INTRODUCTORY SECTION
SPECIAL PANEL: THE PRESS STRIKES BACK
SESSION 1: PLENARY
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SESSION 2: SYSTEM TEST-LECTURE SERIES
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SESSION 3: ATE SOFTWARE GENERATION
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SESSION 4: DEFECT BEHAVIOR AND ANALYSIS TECHNIQUES
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T. M. Eiles, Intel Corporation
K. Wilsher, Schlumberger Technologies
W.K. Lo, Schlumberger Technologies
G. Xiao, Checkpoint Technologies
pp. 80
Will Moore, Dept. Engineering Science
Guido Gronthoud, Philips Research Laboratories
Keith Baker, Philips Research Laboratories
Maurice Lousberg, Philips Research Laboratories
pp. 95
SESSION 5: BIST: INDUSTRIAL APPLICATIONS
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Gundolf Kiefer, University of Stuttgart
Harald Vranken, Philips Research Laboratories
Erik Jan Marinisse, Philips Research Laboratories
Hans-Joachim Wunderlich, University of Stuttgart
pp. 105
Debaleena Das, University of Texas, Austin, TX 78712
Nur A. Touba, University of Texas, Austin, TX 78712 and Cores and System Technology
pp. 115
Michael Cogswell, Test Design Automation, IBM Corp.
Don Pearl, Test Design Automation, IBM Corp.
James Sage, Test Design Automation, IBM Corp.
Alan Troidl, Test Design Automation, IBM Corp.
pp. 123
SESSION 6: MICROPROCESSOR TEST
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Rajesh Raina, Motorola Inc.; Somerset Design Center
Robert Bailey, Motorola Inc.; Somerset Design Center
Dawit Belete, Motorola Inc.; Somerset Design Center
Vikram Khosa, Motorola Inc.; Somerset Design Center
Robert Molyneaux, Motorola Inc.; Somerset Design Center
Javier Prado, Motorola Inc.; Somerset Design Center
Ashutosh Razdan, Motorola Inc.; Somerset Design Center
pp. 132
SESSION 7: SYSTEMS TEST
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Zan Yang, Electrical Engineering Department, Texas A&M University
Byeong Min, Electrical Engineering Department, Texas A&M University
Gwan Choi, Electrical Engineering Department, Texas A&M University
pp. 160
Subhasish Mitra, Stanford University, Stanford, California
Edward J. McCluskey, Stanford University, Stanford, California
pp. 179
SESSION 8: PRACTICALI TESTING FOR DEEP-SUBMICRON DESIGNS
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W. Robert Daasch, LSI Logic Corporation
James McNames, Electrical and Computer Engineering, Portland State University
Daniel Bockelman, Electrical and Computer Engineering, Portland State University
Kevin Cota, Electrical and Computer Engineering, Portland State University
pp. 189
SESSION 9: FAULT DIAGNOSIS ALGORITHMS AND TECHNIQUES
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Xiaoming Yuy, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Jue Wuz, Sun Microsystems, Menlo Park, CA
Elizabeth M. Rudnicky, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 225
Kazuki Shigeta, Analysis Technology Development Division, NEC
Toshio Ishiyama, Analysis Technology Development Division, NEC
pp. 235
Srikanth Venkataraman, Intel Corporation, Hillsboro, OR and Santa Clara, CA
Scott B. Drummonds, Intel Corporation, Hillsboro, OR and Santa Clara, CA
pp. 253
SESSION 10: BIST TECHNIQUES AND APPLICATIONS
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Subrata Roy, Department of ECE University of California
Gokhan Guner, Department of ECE University of California
Kwang-Ting(Tim) Cheng, Department of ECE University of California
pp. 263
Ismet Bayraktaroglu, Computer Science & Engineering Department University of California, San Diego
Alex Orailoglu, Computer Science & Engineering Department University of California, San Diego
pp. 273
Yasuo Sato, Device Development Center, Hitachi, Ltd. , Ome-shi, Tokyo, Japan
Toyohito Ikeya, Device Development Center, Hitachi, Ltd. , Ome-shi, Tokyo, Japan
Michinobu Nakao, Central Research Laboratory, Hitachi, Ltd. , Kokubunnji-shi, Tokyo, Japan
Takaharu Nagumo, Enterprise Server Division, Hitachi, Ltd. , Hadano-shi, Kanagawa, Japan
pp. 283
M.J. Geuzebroek, Delft University of Technology, Faculty of Information Technology and Systems,
J. Th. van de Linden, Scientificial, Delft, The Netherlands
A.J. van de Goor, Delft University of Technology, Faculty of Information Technology and Systems,
pp. 292
SESSION 11: DESIGN VALIDATION: FROM FUNCTION TO TIMING
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Chung-Yang (Ric) Huang, University of California, Santa Barbara
Bwolen Yang, Verplex Systems, Inc.
Huan-Chih Tsai, Verplex Systems, Inc.
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
pp. 309
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, University of Iowa
Seiji Kajihara, Kyushu Institute of Technology
Atsushi Murakami, Kyushu Institute of Technology
Sadami Takeoka, Corporate Semiconductor Development Division
Mitsuyasu Ohta, Corporate Semiconductor Development Division
pp. 317
SESSION 12: DEFECT-BASED TEST METHODOLOGIES AND THE REAL WORLD-LECTURE SERIES
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Edward J. McCluskey, Stanford University, Stanford, CA 94305
Chao-Wen Tseng, Stanford University, Stanford, CA 94305
pp. 336
SESSION 13: TEST TECHNIQUES FOR ADCS
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SESSION 14: DELAY FAULT TESTING
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Atsushi Murakami1, Kyushu Institute of Technology
Seiji Kajihara, Kyushu Institute of Technology
Tsutomu Sasao, Kyushu Institute of Technology
Irith Pomeranz, University of Iowa
Sudhakar M. Reddy, University of Iowa
pp. 376
Manish Sharma, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 385
SESSION 15: OPTIMIZING TEST EFFECTIVENESS
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Peter Maxwell, Agilent Technologies
Ismed Hartanto, Agilent Technologies
Lee Bentz, Agilent Technologies
pp. 400
SESSION 16: MEMORY TESTING
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Ad J. van de Goor, Delft University of Technology, Faculty of Information Technology and Systems
Alexander Paalvast, Delft University of Technology, Faculty of Information Technology and Systems
pp. 426
Harold Pilo, IBM Microelectronics Division
Stu Hall, IBM Microelectronics Division
Patrick Hansen, IBM Microelectronics Division
Steve Lamphier, IBM Microelectronics Division
Chris Murphy, IBM Microelectronics Division
pp. 436
SESSION 17: DEFECT-BASED TEST METHODOLOGIES AND THE REAL WORLD-LECTURE SERIES
null
SESSION 18: FROM TESTER TO APPLICATIONS-BEGINNING TO END
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Jerry Katz, Advantest America R & D Center, Inc.
Rochit Rajsuman, Advantest America R & D Center, Inc.
pp. 468
Jerry J. Broz, Texas Instruments Corporation, Dallas, TX 75243
James C. Andersen, Ph.D, Applied Precision Incorporated, Issaquah, WA 98027
Reynaldo M. Rincon, Texas Instruments Corporation, Dallas, TX 75243
pp. 477
SESSION 19: TESTS FOR CROSSTALK AND BRIDGING FAULTS
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Yi Z hao, University of California, San Diego, La Jolla, CA 92093-0407
Sujit Dey, University of California, San Diego, La Jolla, CA 92093-0407
pp. 492
SESSION 20: ADVANCES IN TEST GENERATION
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Robert Butler, IBM MicroElectronics Division
Brion Keller, IBM MicroElectronics Division
Sarala Paliwal, IBM MicroElectronics Division
Richard Schoonover, IBM MicroElectronics Division
pp. 530
Mark W. Weiss, University of Nebraska-Lincoln
Sharad C. Seth, University of Nebraska-Lincoln
Shashank K. Mehta, Pune University
Kent L. Einspahr, Concordia University
pp. 538
SESSION 21: EMBEDDED MEMORIES TEST AND REPAIR
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Kamran Zarrineh, Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
R. Dean Adams, Design-For-Test Group, IBM Microelectronics, Essex Junction, VT
Thomas J. Eckenrode, Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
Steven P. Gregor, Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
pp. 547
Tomoya Kawagoe, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Jun Ohtani, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Mitsutaka Niiro, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Tukas Ooishi, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Mitsuhiro Hamada, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Hideto Hidaka, Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
pp. 567
SESSION 22: BOARD TEST
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Frans de Jong, Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
Ben Kup, Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
Rodger Schuttert, Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
pp. 575
David McClintock, The University of Texas at Austin
Lance Cunningham, The University of Texas at Austin
Takis Petropoulos, The University of Texas at Austin
pp. 593
SESSION 23: TESTER HARDWARE ISSUES IN LEAPING TO 1GHZ
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Y. Cai, Lucent Technologies - Bell Laboratories
T. P. Warwick, Evaluation and Product Engineering, Inc.
S. G. Rane, Lucent Technologies - Bell Laboratories
E. Masserrat, Lucent Technologies - Bell Laboratories
pp. 600
SESSION 24: SOC TEST SOLUTIONS
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SESSION 25: LOW-POWER BIST
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P. Girard, Universit? Montpellier II / CNRS
L. Guiller, Universit? Montpellier II / CNRS
C. Landrault, Universit? Montpellier II / CNRS
S. Pravossoudovitch, Universit? Montpellier II / CNRS
pp. 652
SESSION 26: METHODOLOGY AND TOOLS FOR MICROPROCESSOR TEST
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Anjali Kinra, Texas Instruments Inc.
Hari Balachandran, Texas Instruments Inc.
Regy Thomas, Texas Instruments Inc.
John Carulli, Texas Instruments Inc.
pp. 701
SESSION 27: BOARD TEST-LECTURE SERIES
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Stephen F. Scheiber, ConsuLogic Consulting Services, 276 Longhouse Lane, Slingerlands, NY 12159-3012
pp. 718
SESSION 28: EXTRACTION TEST AND DIAGNOSIS OF PHYSICAL DEFECTS
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Zoran Stanojevic, Texas A&M University
Hari Balachandran, Texas Instruments, Inc.
D. M. H. Walker, Texas A&M University
Fred Lakhani, International Sematech
Sri Jandhyala, Texas Instruments, Inc.
Jayashree Saxena, Texas Instruments, Inc.
Kenneth M. Butler, Texas Instruments, Inc.
pp. 729
Charles E. Stroud, University of North Carolina at Charlotte
John M. Emmert, University of North Carolina at Charlotte
James R. Bailey, University of Kentucky
Khushru S. Chhor, Cypress Semiconductor
Dragomir Nikolic, Cypress Semiconductor
pp. 760
SESSION 29: USE MODELS OF IEEE P1500
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SESSION 30: QUALITY BIST FOR LOGIC AND FPGA
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Miron Abramovici, Bell Labs - Lucent Technologies
Charles Stroud, Dept. of Electrical Engineering - University of Kentucky
pp. 785
Xiaoling Sun, University of Alberta
Jian Xu, University of Alberta
Ben Chan, University of Alberta
Pieter Trouborst, Microelectronics Group, Nortel Networks
pp. 795
D. Bakalis, Dept. of Computer Engineering and Informatics, University of Patras, Computer Technology Institute, 3, Kolokotroni Str., 262 61 Patras, Greece
D. Nikolos, Dept. of Computer Engineering and Informatics, University of Patras, Computer Technology Institute, 3, Kolokotroni Str., 262 61 Patras, Greece
X. Kavousianos, Dept. of Computer Engineering and Informatics, University of Patras, 26 500, Rio, Greece
pp. 804
SESSION 31: DETECTING ALL TYPES OF FAULTS QUICKLY
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Rao Desineni, Carnegie Mellon University, Pittsburgh, PA 15213
Kumar N. a Dwarkanath, Carnegie Mellon University, Pittsburgh, PA 15213
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA 15213
pp. 812
Srivaths Ravi, Princeton University, Princeton, NJ 08544
Ganesh Lakshminarayana, NEC USA, Inc., Princeton, NJ 08536
Niraj K. Jha, Princeton University, Princeton, NJ 08544
pp. 829
SESSION 32: FPGA TESTING-LECTURE SERIES
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SESSION 33: TEST TECHNIQUES FOR LOW-POWER OPTIMIZATION
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Bahram Pouya, Motorola, ColdFire Core Technology Center
Alfred L. Crouch, Motorola, ColdFire Core Technology Center
pp. 873
Valentin Muresan, Dublin City University, Ireland
Xiaojun Wang, Dublin City University, Ireland
Valentina Muresan, "Politehnica" University of Timisoara, Romania
Mircea Vladutiu, "Politehnica" University of Timisoara, Romania
pp. 882
SESSION 34: TEST ACCESS DESIGN FOR SOC'S
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Erik Jan Marinissen, Philips Research Laboratories
Sandeep Kumar Goel, Indian Institute of Technology
Maurice Lousberg, Philips Research Laboratories
pp. 911
SESSION 35: HOW DO WE KNOW IF FAULT MODELS ARE ACCURATE?
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Jennifer Dworak, Texas A&M University, College Station, Texas
Micheal R. Grimaila, Texas A&M University, College Station, Texas
Sooryong Lee, Texas A&M University, College Station, Texas
Li-C. Wang, Texas A&M University, College Station, Texas
M. Ray Mecer, Texas A&M University, College Station, Texas
pp. 930
SESSION 36: HIGH-FREQUENCY TEST TECHNIQUES
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Takahiro J. Yamaguchi, Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma, Department of Electrical Engineering, University of Washington, Seattle, WA
David Halter, Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Jim Nissen, Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Rajesh Raina, Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Masahiro Ishida, Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Toshifumi Watanabe, Advantest Corporation, Ora, Gunma, Japan
pp. 955
SESSION 37: CONCURRENT ERROR DETECTION
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Subhasish Mitra, Stanford University, Stanford, California
Edward J. McCluskey, Stanford University, Stanford, California
pp. 985
SESSION 38: THE FINAL HURDLE-SIGNALS AND POWER TO THE DUT
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SESSION 39: MIXED-SIGNAL BIST
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Jiun-Lang Huang, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
pp. 1021
Anna Maria Brosa, Electronics Dept. Universitat Polit?cnica de Catalunya
Joan Figueras, Electronics Dept. Universitat Polit?cnica de Catalunya
pp. 1041
SESSION 40: NEW METHODS FOR DELAY TESTING
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Ali Keshavarzi, Microprocessor Research Labs, Intel Corporation
Kaushik Roy, Purdue University,
Manoj Sachdev, University of Waterloo,
Charles F. Hawkins, The University of New Mexico
K. Soumyanath, Microprocessor Research Labs, Intel Corporation
Vivek De, Microprocessor Research Labs, Intel Corporation
pp. 1051
Seonki Kim, University of Minnesota, Minneapolis, Minnesota
Sreejit Chakravarty, Intel Corporation
Bapiraju Vinnakota, University of Minnesota, Minneapolis, Minnesota
pp. 1060
Jim Plusquellic, Department of CSEE, University of Maryland, Baltimore County
Amy Germida, Department of CSEE, University of Maryland, Baltimore County
Jonathan Hudson, Department of CSEE, University of Maryland, Baltimore County
Ernesto Staroswiecki, Department of CSEE, University of Maryland, Baltimore County
Chintan Patel, Department of CSEE, University of Maryland, Baltimore County
pp. 1070
SESSION 41: PROCESSOR CORE TEST TECHNIQUES
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Wei-Cheng Lai, Department of ECE, University of California, Santa Barbara, CA 93106
Angela Krstic, Department of ECE, University of California, Santa Barbara, CA 93106
Kwang-Ting (Tim) Cheng, Department of ECE, University of California, Santa Barbara, CA 93106
pp. 1080
PANEL 1: FUTURE CHALLENGES FOR SYSTEM TEST
PANEL 2: INTERNAL CAD + EDA + SERVICES = TURMOIL, FENCING OR BLISS
Ismed Hartanto, Agilent Technologies, Santa Clara, CA
pp. 1110
PANEL 3: NOISE: WHOSE PROBLEM IS IT ANYWAY?
Sandeep Gupta, Department of EE-Systems, USC, Los Angeles, CA
pp. 1113
Bill Grundmann, Compaq Computer Corporation
pp. 1115
Sandip Kundu, Intel Corporation, MS AN1-2B17
pp. 1116
Nagaraj NS, Texas Instruments Inc.,
pp. 1117
PANEL 4: DFT-FOCUSED CHIP TESTERS: WHAT CAN THEY REALLY DO?
Gordon D Robinson, Credence Systems Corporation, Fremont CA
pp. 1119
PANEL 5: WHAT DEFECTS ESCAPE OUR TESTS . . . AND HOW WILL WE DETECT THEM IN THE FUTURE?
Anjali Kinra, Texas Instruments Inc., 12203 Southwest Fwy, MS 706, Bldg2, Stafford TX 77477
pp. 1124
PANEL 6: GOOD DIE IN BAD NEIGHBORHOODS
Jeffrey L. Roehr, Analog Devices, Wilmington Mass.
pp. 1126
Stefan Eichenberger, Philips Semiconductors, CH-8045 Zurich, Switzerland
pp. 1127
Adit D. Singh, Department of Electrical & Computer Engineering
pp. 1129
PANEL 7: TESTING CHALLENGES FOR MEMS
N. R. Aluru, University of Illinois at Urbana-Champaign, Urbana, IL 61801
pp. 1131
Stephen F. Bart, Microcosm Technologies, Inc., 215 First St. Cambridge, MA 02142, sbart@memcad.com
pp. 1132
R. D. (Shawn) Blanton, Carnegie Mellon University
pp. 1133
Karl F. B?hringer, University of Washington, Seattle, WA
pp. 1134
Richard B. Brown, 2403 EECS, University of Michigan, Ann Arbor, MI 48109-2122
pp. 1135
PANEL 8: WIRELESS COMMUNICATION PRODUCTS MEANS A SYSTEM-ON-CHIP WITH RF HEADACHES FOR TESTING. WHERE IS THE MIRACLE PILL?
PANEL 9: BIG-IRON TESTERS ARE A REALITY-THEIR REQUIREMENTS AND ROLE
PANEL 10: CAN DFT TOTALLY ELIMINATE THE TRADITIONAL FUNCTIONAL TESTING?
Burnell G. West, Schlumberger Semiconductor Solutions San Jose, California, USA
pp. 1146
1999 ITC BEST PAPER:
Peter Maxwell, Hewlett-Packard Company
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Rob Aitken, Hewlett-Packard Company
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Minh Quac, Hewlett-Packard Company
pp. 1148
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