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International Test Conference 1999 (ITC'99)
A DFT Technique for High Performance Circuit Testing
Atlantic City, NJ
September 28-September 30
ISBN: 0-7803-5753-1
Mansour Shashaani, University of Waterloo
Manoj Sachdev, University of Waterloo
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. In addition, various implementations aspects of this technique are also addressed.
Citation:
Mansour Shashaani, Manoj Sachdev, "A DFT Technique for High Performance Circuit Testing," itc, pp.276, International Test Conference 1999 (ITC'99), 1999
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