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International Test Conference 1999 (ITC'99)
A DFT Technique for High Performance Circuit Testing
Atlantic City, NJ
September 28-September 30
ISBN: 0-7803-5753-1
| ASCII Text | x | ||
| Mansour Shashaani, Manoj Sachdev, "A DFT Technique for High Performance Circuit Testing," 2012 IEEE International Test Conference, pp. 276, International Test Conference 1999 (ITC'99), 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/TEST.1999.805641, author = {Mansour Shashaani and Manoj Sachdev}, title = {A DFT Technique for High Performance Circuit Testing}, journal ={2012 IEEE International Test Conference}, volume = {0}, year = {1999}, issn = {1089-3539}, pages = {276}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.1999.805641}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Test Conference TI - A DFT Technique for High Performance Circuit Testing SN - 1089-3539 SP EP A1 - Mansour Shashaani, A1 - Manoj Sachdev, PY - 1999 KW - null VL - 0 JA - 2012 IEEE International Test Conference ER - | |||
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. In addition, various implementations aspects of this technique are also addressed.
Citation:
Mansour Shashaani, Manoj Sachdev, "A DFT Technique for High Performance Circuit Testing," itc, pp.276, International Test Conference 1999 (ITC'99), 1999
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