- I
- ITC
- 1998
- International Test Conference 1998 (ITC'98)
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International Test Conference 1998 (ITC'98)
Washington, D.C. USA
October 18-October 23
ISBN: 0-7803-5093-6
Table of Contents
 | INTRODUCTORY SECTION |
Steering Committee and Subcommittees
| SESSION 1: PLENARY |
| SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES |
| SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION |
| SESSION 4: DFT IN PRACTICE |
| SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST |
| SESSION 6: EMBEDDED CORES |
Sujit Dey, University of California at San Diego
pp. 130
| SESSION 7: BIST SYNTHESIS |
Han Bin Kim, Virginia Polytechnic Institute and State University
Dong Sam Ha, Virginia Polytechnic Institute and State University
pp. 154
| SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING |
| SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS |
| SESSION 10: MIXED-SIGNAL TEST TECHNIQUES |
| SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS |
| SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES |
| SESSION 13: TEST SYNTHESIS |
Y. L. Wu, Chinese University of Hong-Kong
pp. 322
| SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES |
| SESSION 15: BOARD AND SYSTEM TEST |
| SESSION 16: RECENT ADVANCES IN BIST |
| SESSION 17: INTRODUCTION TO MEMS |
| SESSION 18: ADVANCES IN EMBEDDED CORE TEST |
Joep Aerts, Philips Research Laboratories and Eindhoven University of Technology
pp. 448
Hiroshi Date, Institute of Systems & Information Technologies/KYUSHU
pp. 465
| SESSION 19: MICROPROCESSOR TESTING |
| SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES |
| SESSION 21: CONCURRENT CHECKING |
| SESSION 22: MEMS FAULT MODELING AND DIAGNOSIS |
| SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES |
| SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE |
| SESSION 25: PRACTICAL ATPG |
| SESSION 26: DFT THEORY |
| SESSION 27: MIXED-SIGNAL DFT |
| SESSION 29: MICROPROCESSOR TEST TOOLS |
| SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS |
| SESSION 31: SYSTEM LEVEL TEST TECHNIQUES AND PROCESSES |
| SESSION 32: THE NEED FOR SPEED mdash; TIMING AND JITTER TESTING |
| SESSION 33: VECTORS, INTERFACE, PROBES; ATE ISSUES IN AT-SPEED TEST |
Q. Zhou, Georgia Institute of Technology
pp. 824
W. Mertin, Gerhard-Mercator-Universit?t Duisburg
A. Leyk, Gerhard-Mercator-Universit?t Duisburg
U. Behnke, Gerhard-Mercator-Universit?t Duisburg
pp. 843
| SESSION 34: MANUFACTURING PROCESS MONITORING |
Jianlin Yu, University of California at Santa Cruz
pp. 862
| SESSION 35: FAULT DETECTION AND IDDQ |
| SESSION 36: ON-LINE TESTING |
| SESSION 37: CREATING EFFECTIVE TEST SEQUENCES |
| SESSION 38: TEST STANDARDS mdash; STILL EVOLVING |
| SESSION 39: DESIGN VALIDATION AND DIAGNOSIS |
| SESSION 40: ALTERNATIVES TO IDDQ |
| SESSION 41: BIST GENERATOR AND ARCHITECTURES |
| SESSION 42: NEW IDEAS IN LOGIC DIAGNOSIS |
| SESSION 43: EMBEDDED MEMORIES |
Hai Pham, Bell Laboratories - Lucent Technologies
pp. 1112
| PANEL 1: GOOD ENOUGH QUALITY mdash; WHEN IS ?ENOUGH? ENOUGH? |
| PANEL 2: TWO WORLDS COLLIDE: MIXED SIGNAL ASIC TESTING |
| PANEL 3: DIAGNOSTIC WAR STORIES: WHAT SAVED THE DAY? A TECHNIQUE DEBATE |
| PANEL 4: SCALING DEEPER TO SUBMICRON: ON-LINE TESTING TO THE RESCUE |
| PANEL 5: THE ROAD TO SYSTEM-ON-CHIP TEST mdash; IT?S A MATTER OF CORES mdash; IS IT? |
| PANEL 6: BIST VS. ATE: WHICH IS BETTER, FOR WHICH IC TESTS? |
| PANEL 7: HOW REAL IS THE NEW 1997 SIA ROADMAP? |
| PANEL 8: ACADEMIC RESEARCH: POWER PLANT OR IVORY TOWER? |
| PANEL 9: FLYING PROBERS mdash; A NEW ERA IN LOADED BOARD FIXTURELESS TEST |
| PANEL 10: STUCK-AT FAULT: THE FAULT MODEL OF CHOICE FOR THE THIRD MILLENNIUM!? |
| BEST PAPER: |
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