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International Test Conference 1998 (ITC'98)
Washington, D.C. USA
October 18-October 23
ISBN: 0-7803-5093-6
Table of Contents
INTRODUCTORY SECTION
Steering Committee and Subcommittees
SESSION 1: PLENARY
SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES
SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION
Kamran Zarrineh, State University of New York at Buffalo
Shambhu J. Upadhyaya, State University of New York at Buffalo
Sreejit Chakravarty, Intel Corporation
pp. 73
SESSION 4: DFT IN PRACTICE
Pamela Gillis, IBM Microelectronics Division
Francis Woytowich, IBM Microelectronics Division
Kevin McCauley, IBM Test Design Automation
Ulrich Baur, IBM System/390 Division
pp. 83
SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST
Andreas C. Pfahnl, Kinetrix, Inc.
John H. Lienhard V, Massachusetts Institute of Technology
Alexander H. Slocum, Massachusetts Institute of Technology
pp. 109
Andreas C. Pfahnl, Kinetrix, Inc.
John H. Lienhard V, Massachusetts Institute of Technology
Alexander H. Slocum, Massachusetts Institute of Technology
pp. 114
Mark Malinoski, Schlumberger Test & Transactions
James Maveety, Intel Corporation
Steve Knostman, Schlumberger Test & Transactions
Tom Jones, Schlumberger Test & Transactions
pp. 119
SESSION 6: EMBEDDED CORES
Yervant Zorian, LogicVision
Erik Jan Marinissen, Philips Research
Sujit Dey, University of California at San Diego
pp. 130
SESSION 7: BIST SYNTHESIS
Zhe Zhao, University of Texas at Austin
Bahram Pouya, University of Texas at Austin and Motorola
Nur A. Touba, University of Texas at Austin
pp. 144
Han Bin Kim, Virginia Polytechnic Institute and State University
Takeshi Takahashi, Advantest America R&D Center Inc.
Dong Sam Ha, Virginia Polytechnic Institute and State University
pp. 154
SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING
Anne E. Gattiker, Carnegie Mellon University
Wojciech Maly, Carnegie Mellon University
pp. 174
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS
Alex Biewenga, Philips Electronic Design and Tools
Math Muris, Philips Electronic Design and Tools
Rodger Schuttert, Philips Electronic Design and Tools
Urs Fawer, Philips Semiconductors AG
pp. 222
D.C. Keezer, Georgia Institute of Technology
K.E. Newman, Georgia Institute of Technology
J.S. Davis, Georgia Institute of Technology
pp. 228
Bruce C. Kim, Michigan State University
David Keezer, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
pp. 234
SESSION 10: MIXED-SIGNAL TEST TECHNIQUES
S. Sasho, Asahi Kasei Microsystems Co.
M. Shibata, Asahi Kasei Microsystems Co.
pp. 258
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS
Toshinori Ishii, Mitsubishi Materials Corp.
Hideaki Yoshida, Mitsubishi Materials Corp.
pp. 272
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES
Erik Jan Marinissen, Philips Research Laboratories
Robert Arendsen, Philips Semiconductors
Gerard Bos, Philips Semiconductors
Hans Dingemanse, Philips Semiconductors
Maurice Lousberg, Philips Research Laboratories
Clemens Wouters, Philips Semiconductors
pp. 284
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
pp. 313
SESSION 13: TEST SYNTHESIS
W. B. Jone, National Chung-Cheng University
J. C. Rau, National Chung-Cheng University
S. C. Chang, National Chung-Cheng University
Y. L. Wu, Chinese University of Hong-Kong
pp. 322
SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES
SESSION 15: BOARD AND SYSTEM TEST
SESSION 16: RECENT ADVANCES IN BIST
Charles Stroud, University of Kentucky
Sajitha Wijesuriya, University of Kentucky
Carter Hamilton, University of Kentucky
Miron Abramovici, Bell Labs - Lucent Technologies
pp. 404
Nilanjan Mukherjee, Bell Laboratories, Lucent Technologies
Tapan J. Chakraborty, Bell Laboratories, Lucent Technologies
Sudipta Bhawmik, Bell Laboratories, Lucent Technologies
pp. 422
SESSION 17: INTRODUCTION TO MEMS
SESSION 18: ADVANCES IN EMBEDDED CORE TEST
Joep Aerts, Philips Research Laboratories and Eindhoven University of Technology
Erik Jan Marinissen, Philips Research Laboratories
pp. 448
SESSION 19: MICROPROCESSOR TESTING
Anjali Kinra, Texas Instruments Inc.
Aswin Mehta, Texas Instruments Inc.
Neal Smith, Texas Instruments Inc.
Jackie Mitchell, Texas Instruments Inc.
Fred Valente, Texas Instruments Inc.
pp. 480
Dilip K. Bhavsar, Compaq Computer Corporation
David R. Akeson, Compaq Computer Corporation
Michael K. Gowan, Compaq Computer Corporation
Daniel B. Jackson, Compaq Computer Corporation
pp. 487
SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES
Ed Chang, Credence Systems Corporation
David Cheung, Credence Systems Corporation
Robert Huston, Credence Systems Corporation
Jim Seaton, Credence Systems Corporation
Gary Smith, Credence Systems Corporation
pp. 500
SESSION 21: CONCURRENT CHECKING
SESSION 22: MEMS FAULT MODELING AND DIAGNOSIS
Abhijeet Kolpekwar, Carnegie Mellon University
Chris Kellen, Carnegie Mellon University
R. D.(Shawn) Blanton, Carnegie Mellon University
pp. 557
SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES
SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE
SESSION 25: PRACTICAL ATPG
Weiyu Chen, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 641
SESSION 26: DFT THEORY
Shih-Chieh Chang, National Chung Cheng University
Shi-Sen Chang, National Chung Cheng University
Wen-Ben Jone, National Chung Cheng University
Chien-Chung Tsai, Mentor Graphics Corp.
pp. 658
Yiorgos Makris, University of California at San Diego
Alex Orailaglu, University of California at San Diego
pp. 668
SESSION 27: MIXED-SIGNAL DFT
SESSION 29: MICROPROCESSOR TEST TOOLS
SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS
Dan Knebel, IBM T.J. Watson Research
Pia Sanda, IBM T.J. Watson Research
Moyra MC Manus, IBM T.J. Watson Research
J. A. Kash, IBM T.J. Watson Research
J. C. Tsang, IBM T.J. Watson Research
Dave Vallett, IBM Microelectronics
Leendert Huisman, IBM Microelectronics
Phil Nigh, IBM Microelectronics
Franco Motika, Micrus Corporation
pp. 733
Jayashree Saxena, Texas Instruments Inc.
Kenneth M. Butler, Texas Instruments Inc.
Hari Balachandran, Texas Instruments Inc.
David B. Lavo, University of California at Santa Cruz
Tracy Larrabee, University of California at Santa Cruz
F. Joel Ferguson, University of California at Santa Cruz
Brian Chess, Hewlett-Packard Corp.
pp. 748
SESSION 31: SYSTEM LEVEL TEST TECHNIQUES AND PROCESSES
A. Benso, Politecnico di Torino
P. Prinetto, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
pp. 768
Chauchin Su, National Central University
Shung-Won Jeng, National Central University
Yue-Tsang Chen, National Central University
pp. 774
Moshe Ben-Bassat, IET Intelligent Electronics
Israel Beniaminy, IET Intelligent Electronics
David Joseph, IET Intelligent Electronics
pp. 793
SESSION 32: THE NEED FOR SPEED mdash; TIMING AND JITTER TESTING
SESSION 33: VECTORS, INTERFACE, PROBES; ATE ISSUES IN AT-SPEED TEST
W. Mertin, Gerhard-Mercator-Universit?t Duisburg
A. Leyk, Gerhard-Mercator-Universit?t Duisburg
U. Behnke, Gerhard-Mercator-Universit?t Duisburg
V. Wittpahl, Gerhard-Mercator-Universit?t Duisburg
pp. 843
SESSION 34: MANUFACTURING PROCESS MONITORING
Dilip K. Bhavsar, Compaq Computer Corporation
Ugonna Echeruo, Compaq Computer Corporation
David R. Akeson, Compaq Computer Corporation
William J. Bowhill, Compaq Computer Corporation
pp. 853
T. M. Mak, Intel Corporation
Debika Bhattacharya, Intel Corporation
Cheryl Prunty, Intel Corporation
Bob Roeder, Intel Corporation
Nermine Ramadan, Intel Corporation
Joel Ferguson, University of California at Santa Cruz
Jianlin Yu, University of California at Santa Cruz
pp. 862
Ivo Schanstra, Philips Semiconductors
Dharmajaya Lukita, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Kees Veelenturf, Philips Semiconductors
Paul J. van Wijnen, Philips Semiconductors
pp. 872
SESSION 35: FAULT DETECTION AND IDDQ
Yukio Okuda, Semiconductor Company, Sony Corp.
Isao Kubota, Semiconductor Company, Sony Corp.
Masahiro Watanabe, Semiconductor Company, Sony Corp.
pp. 900
SESSION 36: ON-LINE TESTING
SESSION 37: CREATING EFFECTIVE TEST SEQUENCES
Ilker Hamzaoglu, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 944
SESSION 38: TEST STANDARDS mdash; STILL EVOLVING
SESSION 39: DESIGN VALIDATION AND DIAGNOSIS
SESSION 40: ALTERNATIVES TO IDDQ
Bapiraju Vinnakota, University of Minnesota
Wanli Jiang, University of Minnesota
Dechang Sun, University of Minnesota
pp. 1027
SESSION 41: BIST GENERATOR AND ARCHITECTURES
Janusz Rajski, Mentor Graphics Corporation
Nagesh Tamarapalli, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
pp. 1047
Huan-Chih Tsai, University of California at Santa Barbara
Sudipta Bhawmik, Bell Laboratories, Lucent Technologies
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
pp. 1065
SESSION 42: NEW IDEAS IN LOGIC DIAGNOSIS
David B. Lavo, University of California at Santa Cruz
Brian Chess, University of California at Santa Cruz
Tracy Larrabee, University of California at Santa Cruz
Ismed Hartanto, Hewlett-Packard Company
pp. 1084
Vamsi Boppana, Fujitsu Laboratories of America, Inc.
Masahiro Fujita, Fujitsu Laboratories of America, Inc.
pp. 1094
SESSION 43: EMBEDDED MEMORIES
Ilyoung Kim, Bell Laboratories - Lucent Technologies
Yervant Zorian, Bell Laboratories - Lucent Technologies
Goh Komoriya, Bell Laboratories - Lucent Technologies
Hai Pham, Bell Laboratories - Lucent Technologies
Frank P. Higgins, Bell Laboratories - Lucent Technologies
Jim L. Lewandowski, Bell Laboratories - Lucent Technologies
pp. 1112
Roderick McConnell, Siemens Semiconductor
Udo Möller, Siemens Semiconductor
Detlev Richter, Siemens Semiconductor
pp. 1120
PANEL 1: GOOD ENOUGH QUALITY mdash; WHEN IS ?ENOUGH? ENOUGH?
William R. Simpson, Institute for Defense Analyses
pp. 1127
PANEL 2: TWO WORLDS COLLIDE: MIXED SIGNAL ASIC TESTING
Mark Burns, Texas Instruments, Inc.
pp. 1132
Ken Lanier, LTX Corporation
pp. 1133
PANEL 3: DIAGNOSTIC WAR STORIES: WHAT SAVED THE DAY? A TECHNIQUE DEBATE
PANEL 4: SCALING DEEPER TO SUBMICRON: ON-LINE TESTING TO THE RESCUE
PANEL 5: THE ROAD TO SYSTEM-ON-CHIP TEST mdash; IT?S A MATTER OF CORES mdash; IS IT?
PANEL 6: BIST VS. ATE: WHICH IS BETTER, FOR WHICH IC TESTS?
Satoru Tanoi, OKI Electric Industry Co., Ltd.
pp. 1149
PANEL 7: HOW REAL IS THE NEW 1997 SIA ROADMAP?
PANEL 8: ACADEMIC RESEARCH: POWER PLANT OR IVORY TOWER?
PANEL 9: FLYING PROBERS mdash; A NEW ERA IN LOADED BOARD FIXTURELESS TEST
PANEL 10: STUCK-AT FAULT: THE FAULT MODEL OF CHOICE FOR THE THIRD MILLENNIUM!?
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 1166
BEST PAPER:
Anne E. Gattiker, Carnegie Mellon University
Wojciech Maly, Carnegie Mellon University
pp. 1168
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