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International Test Conference 1998 (ITC'98)
ANALYSIS OF PATTERN-DEPENDENT AND TIMING-DEPENDENT FAILURES IN AN EXPERIMENTAL TEST CHIP
Washington, D.C. USA
October 18-October 23
ISBN: 0-7803-5093-6
Jonathan T.-Y. Chang, Stanford University
Chao-Wen Tseng, Stanford University
Chien-Mo James Li, Stanford University
Mike Purtell, Advantest America R&D Center, Inc.
Edward J. McCluskey, Stanford University
This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery.
Citation:
Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey, "ANALYSIS OF PATTERN-DEPENDENT AND TIMING-DEPENDENT FAILURES IN AN EXPERIMENTAL TEST CHIP," itc, pp.184, International Test Conference 1998 (ITC'98), 1998
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