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International Test Conference 1997 (ITC'97)
Washington D.C.
November 01-November 06
ISBN: 0-7803-4210-0
Table of Contents
INTRODUCTORY SECTION
SESSION 1: PLENARY
SESSION 2: DYNAMIC CURRENT TESTING
Edward I. Cole Jr., Sandia National Laboratories
Jerry M. Soden, Sandia National Laboratories
Paiboon Tangyunyong, Sandia National Laboratories
Patrick L. Candelaria, Sandia National Laboratories
Richard W. Beegle, Sandia National Laboratories
Daniel L. Barton, Sandia National Laboratories
Christopher L. Henderson, Sandia National Laboratories
Charles F. Hawkins, University of New Mexico
pp. 23
J. S. Beasley, New Mexico State University
A. W. Righter, Sandia National Laboratories
C. J. Apodaca, Intel Corporation
S. Pour-Mozafari, New Mexico State University
D. Huggett, New Mexico State University
pp. 32
SESSION 3: EMBEDDED CORE TESTING
SESSION 4: ATE HARDWARE IMPROVEMENTS FOR HIGH-SPEED TEST
Takahiro Yamaguchi, Advantest Laboratories Ltd.
Marco Tilgner, Tokyo Institute of Technology
Masahiro Ishida, Advantest Laboratories Ltd.
Dong Sam Ha, Virginia Polytechnic Institute and State University
pp. 79
SESSION 5: MCM SYSTEMS TEST
Thomas G. Foote, International Business Machines Corporation
Dale E. Hoffman, International Business Machines Corporation
William V. Huott, International Business Machines Corporation
Timothy J. Koprowski, International Business Machines Corporation
Bryan J. Robbins, International Business Machines Corporation
Mary P. Kusko, IBM Microelectronics
pp. 106
Otto A. Torreiter, IBM Development Lab Germany
Ulrich Baur, IBM Development Lab Germany
Georg Goecke, IBM Development Lab Germany
Kevin Melocco, IBM Microelectronics
pp. 115
SESSION 6: UNPOWERED OPENS LECTURE SERIES
Ted T. Turner, Hewlett-Packard Company
pp. 124
SESSION 7: IDDQ TESTING
Antoni Ferré, Universitat Politècnica de Catalunya
Joan Figueras, Universitat Politècnica de Catalunya
pp. 136
Anne E. Gattiker, Carnegie Mellon University
Wojciech Maly, Carnegie Mellon University
pp. 156
SESSION 8: PROGRESS ON STANDARDS AND BENCHMARKS
B. Kaminska, Opmaxx, Inc.
K. Arabi, Opmaxx, Inc.
I. Bell, University of Hull
P. Goteti, University of Washington
J. L. Huertas, CNM, Seville
B. Kim, Tufts University
A. Rueda, CNM, Seville
M. Soma, University of Washington
pp. 183
SESSION 9: MEMORY TEST
Theo J. Powell, Texas Instruments, Inc.
Francis Hii, Texas Instruments Singapore, PTE. LTD.
Dan Cline, Texas Instruments, Inc.
pp. 200
SESSION 10: TEST SYNTHESIS
SESSION 11: UNPOWERED OPENS LECTURE SERIES
SESSION 12: MICROPROCESSOR TEST I
Carol Stolicny, Digital Semiconductor
Richard Davies, Digital Semiconductor
Pamela McKernan, Digital Semiconductor
Tuyen Truong, Digital Semiconductor
pp. 278
SESSION 13: DIAGNOSIS & FAILURE ANALYSIS LECTURE SERIES
SESSION 14: DETERMINISTIC BIST
Krishnendu Chakrabarty, Boston University
Brian T. Murray, General Motors R&D Center
Jian Liu, Boston University
Minyao Zhu, Boston University
pp. 328
Christophe FAGOT, UNIVERSITE MONTPELLIER II
Patrick GIRARD, UNIVERSITE MONTPELLIER II
Christian LANDRAULT, UNIVERSITE MONTPELLIER II
pp. 338
SESSION 15: COMPONENTS FOR MCMS: KNOWN-GOOD-DIE AND SUBSTRATES
SESSION 16: MIXED-SIGNAL SEMINAR: MEASUREMENT TECHNIQUES
SESSION 17: MICROPROCESSOR TEST II
SESSION 18: DIAGNOSIS AND FAILURE ANALYSIS LECTURE SERIES PANEL
Jerry M. Soden, Sandia National Laboratories
Christopher L. Henderson, Sandia National Laboratories
pp. 435
SESSION 19: DESIGN FOR DELAY TEST
Angela Krstić, University of California at Santa Barbara
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
pp. 436
Ramesh C. Tekumalla, University of Massachusetts at Amherst
Prem R. Menon, University of Massachusetts at Amherst
pp. 454
SESSION 20: CONCURRENT CHECKING
A. L. Burress, North Carolina A&T State University
P. K. Lala, North Carolina A&T State University
pp. 471
C. Stroud, University of Kentucky
M. Ding, University of Kentucky
S. Seshadri, University of Kentucky
I. Kim, Lucent Technologies
S. Roy, Lucent Technologies
S. Wu, Lucent Technologies
R. Karri, Lucent Technologies
pp. 479
SESSION 21: MIXED-SIGNAL SEMINAR: MEASUREMENTS USING P1149.4
Kenneth P. Parker, Hewlett Packard Company
John E. McDermid, Hewlett Packard Company
Rodney A. Browen, Hewlett Packard Company
Kozo Nuriya, Matsushita Electric Industrial Co., Ltd.
Katsuhiro Hirayama, Matsushita Electric Industrial Co., Ltd.
Akira Matsuzawa, Matsushita Electric Industrial Co., Ltd.
pp. 489
Chauchin Su, National Central University
Yue-Tsang Chen, National Central University
Shyh-Jye Jou, National Central University
pp. 499
SESSION 22: HIGH-PERFORMANCE PROBES AND SOCKETS
SESSION 23: BIST AND DFT ECONOMICS
Charles Stroud, University of Kentucky
Eric Lee, University of Kentucky
Miron Abramovici, Bell Labs - Lucent Technologies
pp. 539
Kun-Han Tsai, University of California at Santa Barbara
Janusz Rajski, Mentor Graphics Corporation
Malgorzata Marek-Sadowska, University of California at Santa Barbara
pp. 548
S. Wei, Carnegie Mellon University
P. K. Nag, Carnegie Mellon University
R. D. Blanton, Carnegie Mellon University
A. Gattiker, Carnegie Mellon University
W. Maly, Carnegie Mellon University
pp. 557
SESSION 24: ON-LINE TESTING TECHNIQUES FOR VLSI
E. Böhl, Robert Bosch GmbH
Th. Lindenkreuz, Robert Bosch GmbH
R. Stephan, Robert Bosch GmbH
pp. 567
Cecilia Metra, University of Bologna
Michele Favalli, University of Bologna
Bruno Riccó, University of Bologna
pp. 587
SESSION 25: DEFECT BEHAVIOR, TEST EFFICIENCY AND FAULT MODEL EXTENSION
M. Renovell, Universit? de Montpellier II
Y. Bertrand, Universit? de Montpellier II
pp. 607
Thomas Bartenstein, International Business Machines Corp.
Gilbert Vandling, International Business Machines Corp.
pp. 617
SESSION 26: MIXED-SIGNAL SEMINAR PANEL: ON-CHIP 1149.4, WHAT FOR?
SESSION 27: BOARD-LEVEL TEST METHODS
Jiun-Lang Huang, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
pp. 640
SESSION 28: SOFTWARE FOR NEW TEST STRATEGIES
SESSION 29: DESIGN-FOR-TEST TOPICS
Nilanjan Mukherjee, Lucent Technologies
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznali University of Technology
pp. 694
SESSION 30: SEQUENTIAL ATPG
Elizabeth M. Rudnick, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 723
M. H. Konijnenburg, Delft University of Technology
J.Th. van der Linden, Delft University of Technology
A. J. van de Goor, Delft University of Technology
pp. 733
SESSION 31: MIXED-SIGNAL SEMINAR: BIST/DFT
Mani Soma, University of Washington
Thomas M. Bocek, Boeing Defense and Space Group
Tuyen D. Vu, Boeing Defense and Space Group
Jason D. Moffatt, Boeing Defense and Space Group
pp. 768
SESSION 32: TEST ENGINEERING TOPICS
Weiyu Chen, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 809
SESSION 33: TOOLS AND TECHNIQUES FOR DEFECT TESTING
SESSION 34: SPECIALIZED BIST GENERATORS
Seongmoon Wang, University of Southern California
Sandeep K. Gupta, University of Southern California
pp. 848
J. Li, University of Alberta Edmonton
X. Sun, University of Alberta Edmonton
K. Soon, University of Alberta Edmonton
pp. 858
SESSION 35: ADVANCES IN DIGITAL LOGIC DIAGNOSIS
David B. Lavo, University of California at Santa Cruz
Brian Chess, Hewlett-Packard Corp.
Tracy Larrabee, University of California at Santa Cruz
F. Joel Ferguson, University of California at Santa Cruz
Jayashree Saxena, Texas Instruments Inc.
Kenneth M. Butler, Texas Instruments Inc.
pp. 887
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznań University of Technology
pp. 894
SESSION 36: MIXED-SIGNAL SEMINAR: FAULT MODELING
R. Voorakaranam, Georgia Institute of Technology
S. Chakrabarti, Georgia Institute of Technology
J. Hou, Georgia Institute of Technology
A. Gomes, Georgia Institute of Technology
S. Cherubal, Georgia Institute of Technology
A. Chatterjee, Georgia Institute of Technology
W. Kao, Cadence Design Systems
pp. 903
Chen-Yang Pan, University of California at Santa Barbara
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
pp. 913
SESSION 37: NEW FRONTIERS IN TEST
SESSION 38: DESIGN VERIFICATION AND DIAGNOSIS
Shi-Yu Huang, National Semiconductor Corp.
Kwang-Ting Cheng, University of California at Santa Barbara
Kuang-Chien Chen, Fujitsu Labs. of America
David Ihsin Cheng, Exemplar Logic Inc.
pp. 974
SESSION 39: DELAY FAULT TESTING
Zhongcheng Li, University of California at Berkeley
Yinghua Min, Chinese Academy of Sciences
Robert K. Brayton, University of California at Berkeley
pp. 992
SESSION 40: TEST LANGUAGE STANDARDS
SESSION 41: ADVANCES IN PROBE TECHNOLOGY
PANEL 2: PARTIAL SCAN IS DEAD. LONG LIVE ALMOST-FULL SCAN!
Jeff Rearick, Hewlett-Packard Company
pp. 1032
PANEL 3: ETHICS, PROFESSIONALISM, AND ACCOUNTABILITY — DOES IT EXIST IN TEST?
PANEL 4: VISION SYSTEMS FOR BOARD TEST: MEETING THEIR PROMISE?
PANEL 6: SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT
Phil Nigh, IBM
Ken Butler, Texas Instruments
Peter Maxwell, Hewlett-Packard
Rob Aitken, Hewlett-Packard
Wojciech Maly, Carnegie Mellon University
pp. 1037
PANEL 7: EMBEDDED CORE TEST PLUG-N-PLAY: IS IT ACHIEVABLE?
PANEL 8: ON-LINE TESTING, INDUSTRIAL PRACTICE AND PERSPECTIVES
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